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IDT70V927S25PRF8

Description
Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP128, TQFP-128
Categorystorage    storage   
File Size194KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

IDT70V927S25PRF8 Overview

Dual-Port SRAM, 32KX16, 25ns, CMOS, PQFP128, TQFP-128

IDT70V927S25PRF8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeQFP
package instructionTQFP-128
Contacts128
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time25 ns
JESD-30 codeR-PQFP-G128
JESD-609 codee0
length20 mm
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals128
word count32768 words
character code32000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX16
Output characteristics3-STATE
ExportableYES
Package body materialPLASTIC/EPOXY
encapsulated codeLFQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE, FINE PITCH
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width14 mm
Base Number Matches1
HIGH-SPEED 3.3V 32K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features
x
x
PRELIMINARY
IDT70V927S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 25/30ns
Low-power operation
– IDT70V927S
Active: 550mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V927L
Active: 550mW (typ.)
Standby: 660mW (typ.)
Flow-Through output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
x
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 25ns clock to data out
– Self-timed write allows fast cycle time
– 30ns cycle time, 33MHz operation
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Available in a 128 pin Thin Quad Flatpack
Functional Block Diagram
R/W
L
UB
L
CE
0L
CE
1L
LB
L
OE
L
R/W
R
UB
R
CE
0R
CE
1R
LB
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
A
14L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3749 drw 01
SEPTEMBER 1999
1
©1999 Integrated Device Technology, Inc.
DSC 3749/4

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