USB97C100QFP datasheet, PDF - EEWORLD Datasheet

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USB97C100QFP: DescriptionUSB Bus Controller, CMOS, PQFP128, QFP-128; CategoryThe embedded processor and controller Microcontrollers and processors; File Size430KB，64 Pages; ManufacturerSMSC; Websitehttp://www.smsc.com/

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USB97C100QFP Overview

USB Bus Controller, CMOS, PQFP128, QFP-128

USB97C100QFP Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	FQFP, QFP128,.67X.93,20
Contacts	128
Reach Compliance Code	unknown
Address bus width	20
Bus compatibility	ISA
maximum clock frequency	24 MHz
Maximum data transfer rate	12 MBps
External data bus width	8
JESD-30 code	R-PQFP-G128
JESD-609 code	e0
length	20 mm
Number of terminals	128
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Encapsulate equivalent code	QFP128,.67X.93,20
Package shape	RECTANGULAR
Package form	FLATPACK, FINE PITCH
Peak Reflow Temperature (Celsius)	235
power supply	3.3/5 V
Certification status	Not Qualified
Maximum seat height	3.4 mm
Maximum slew rate	63 mA
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches	1

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USB97C100

ADVANCE INFORMATION

Multi-Endpoint USB Peripheral Controller

FEATURES

High Performance USB Peripheral Controller

Engine

Integrated USB Transceiver

Serial Interface Engine (SIE)

8051 Microcontroller (MCU)

Patented Memory Management Unit (MMU)

4 Channel 8237 DMA Controller

(ISADMA)

4K Byte On Board USB Packet Buffer

Quasi-ISA Peripheral Interface

USB Bus Snooping Capabilities

GPIOs

Complete USB Specification 1.1 Compatibility

Isochronous, Bulk, Interrupt, and Control

Data Independently Configurable per

Endpoint

Dynamic Hardware Allocation of -Packet

Buffer for Virtual Endpoints

Multiple Virtual Endpoints (up to 16 TX, 16

RX Simultaneously)

Multiple Alternate Address Filters

Dynamic Endpoint Buffer Length

Allocation (0-1280 Byte Packets)

High Speed (12Mbps) Capability

MMU and SRAM Buffer Allow Buffer Optimization

and Maximum Utilization of USB Bandwidth

128 Byte Page Size

10 Pages Maximum per Packet

Up to 16 Deep Receive Packet Queue

Up to 5 Deep Transmit Packet Queue, per

Endpoint

Hardware Generated Packet Header

Records Each Packet Status Automatically

Simultaneous Arbitration Between MCU,

SIE, and ISA DMA Accesses

Extended Power Management

Standard 8051 "Stop Clock" Modes

Additional USB and ISA Suspend

Resume Events

Internal 8MHz Ring Oscillator for Immediate

Low Power Code Execution

24, 16, 12, 8, 4, and 2 MHz PLL Taps For on

the Fly MCU and DMA Clock Switching

Independent Clock/Power Management for

SIE, MMU, DMA and MCU

DMA Capability with ISA Memory

Four Independent Channels

Transfer Between Internal and External

Memory

Transfer Between I/O and Buffer Memory

External Bus Master Capable

External MCU Memory Interface

1M Byte Code and Data Storage via 16K

Windows

Flash, SRAM, or EPROM

Downloadable via USB, Serial Port, or ISA

Peripheral

Quasi-ISA Interface Allows Interface to New and

"Legacy" Peripheral Devices

1M ISA Memory Space via 4K MCU Window

64K ISA I/O Space via 256 Byte MCU

Window

4 External Interrupt Inputs

4 DMA Channels

Variable Cycle Timing

8 Bit Data Path

5V or

3.3v

Operation

On Board Crystal Driver Circuit

128 Pin QFP Package

ORDERING INFORMATION

Order Number: USB97C100QFP

128 Pin QFP Package

SMSC DS – USB97C100

Rev. 01/03/2001

GENERAL DESCRIPTION

The USB97C100 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple

endpoint applications. The USB97C100 provides an ISA-like bus interface, which will allow virtually any PC peripheral to

be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput

disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall

bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing back-

to-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to coexist with

other peripherals such as serial and parallel ports on a single USB link.

The USB97C100 allows external program code to be downloaded over the USB to allow easy implementation of varied

peripheral USB Device Classes and combinations. This also provides a method for convenient field upgrades and

modifications.

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems

Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included

as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although

the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make

changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications

before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any

licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most

recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product

may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly

sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application

where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an

Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well

as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES

ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,

OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON

CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT

ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES.

SMSC DS – USB97C100

Page 2

Rev. 01/03/2001

TABLE OF CONTENTS

FEATURES ................................................................................................................................................................... 1

GENERAL DESCRIPTION............................................................................................................................................ 2

PIN CONFIGURATION ................................................................................................................................................. 4

DESCRIPTION OF PIN FUNCTIONS ........................................................................................................................... 5

BUFFER TYPE DESCRIPTIONS.................................................................................................................................. 7

FUNCTIONAL DESCRIPTION...................................................................................................................................... 9

Serial Interface Engine (SIE)......................................................................................................................................... 9

Micro Controller Unit (MCU) .......................................................................................................................................... 9

SIEDMA......................................................................................................................................................................... 9

Memory Management Unit (MMU) Register Description ............................................................................................... 9

ISADMA......................................................................................................................................................................... 9

Applications ................................................................................................................................................................. 10

TYPICAL SIGNAL CONNECTIONS ............................................................................................................................ 12

MCU MEMORY MAP .................................................................................................................................................. 13

Code Space................................................................................................................................................................. 13

Data Space.................................................................................................................................................................. 13

ISADMA Memory Map ................................................................................................................................................. 13

MCU Block Register Summary.................................................................................................................................... 14

MMU Block Register Summary ................................................................................................................................... 15

SIE Block Register Summary ...................................................................................................................................... 16

MCU REGISTER DESCRIPTION................................................................................................................................ 17

MCU Runtime Registers.............................................................................................................................................. 17

FIFO Status Registers................................................................................................................................................. 20

MCU Power Management Registers ........................................................................................................................... 24

MCU ISA Interface Registers ...................................................................................................................................... 27

8237 (ISADMA) REGISTER DESCRIPTION .............................................................................................................. 30

Memory Map................................................................................................................................................................ 30

Runtime Registers....................................................................................................................................................... 31

MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION ....................................................................... 37

MMU Interface Registers............................................................................................................................................. 37

MMU FREE PAGES REGISTER................................................................................................................................. 40

16 BYTE DEEP TX COMPLETION FIFO REGISTER ................................................................................................ 40

TX FIFO POP REGISTER........................................................................................................................................... 41

SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ............................................................................. 45

Packet Header Definition............................................................................................................................................. 45

SIE Interface Registers ............................................................................................................................................... 46

DC PARAMETERS ..................................................................................................................................................... 51

USB PARAMETERS ................................................................................................................................................... 53

USB DC PARAMETERS ............................................................................................................................................. 53

USB AC PARAMETERS.............................................................................................................................................. 54

MECHANICAL OUTLINE............................................................................................................................................ 63

USB97C100 REVISIONS............................................................................................................................................ 64

SMSC DS – USB97C100

Page 3

Rev. 01/03/2001

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