UPD45128841G5-A75A-9JF datasheet, PDF

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UPD45128841G5-A75A-9JF: DescriptionSynchronous DRAM, 16MX8, 5.4ns, MOS, PDSO54, PLASTIC, TSOP2-54; Categorystorage storage; File Size727KB，85 Pages; ManufacturerELPIDA; Websitehttp://www.elpida.com/en

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UPD45128841G5-A75A-9JF Overview

Synchronous DRAM, 16MX8, 5.4ns, MOS, PDSO54, PLASTIC, TSOP2-54

UPD45128841G5-A75A-9JF Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP54,.46,32
Contacts	54
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
interleaved burst length	1,2,4,8
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	54
word count	16777216 words
character code	16000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16MX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP54,.46,32
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
power supply	3.3 V
Certification status	Not Qualified
refresh cycle	4096
Maximum seat height	1.2 mm
self refresh	YES
Continuous burst length	1,2,4,8,FP
Maximum standby current	0.001 A
Maximum slew rate	0.27 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	MOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD45128441, 45128841

128M-bit Synchronous DRAM

4-bank, LVTTL

Description

The

PD45128441, 45128841 are high-speed 134,217,728-bit synchronous dynamic random-access memories,

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

All inputs and outputs are synchronized with the positive edge of the clock.

The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).

These products are packaged in 54-pin TSOP (II).

Features

•

Pulsed interface

• ×4, ×8

organization

organized as 8,388,608

4, 4,194,304

4 (word

bit

bank), respectively.

•

Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

•

Possible to assert random column address in every cycle

•

Quad internal banks controlled by BA0(A13) and BA1(A12)

•

Programmable Wrap sequence (Sequential / Interleave)

•

Programmable burst length (1, 2, 4, 8 and full page)

•

Programmable /CAS latency (2 and 3)

•

CBR (Auto) refresh and self refresh

•

Single 3.3 V

0.3 V power supply

•

4,096 refresh cycles / 64 ms

•

Automatic precharge and controlled precharge

•

LVTTL compatible inputs and outputs

•

Burst termination by Burst stop command and Precharge command

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for

availability and additional information.

Document No. E0343N10 (Ver. 1.0)

Date Published February 2003 (K) Japan

URL: http://www.elpida.com

This product became EOL in March, 2007.

Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.

©Elpida

Memory, Inc. 2003

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