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UPD45128841G5-A75-9JF

Description
Synchronous DRAM, 16MX8, 5.4ns, MOS, PDSO54, PLASTIC, TSOP2-54
Categorystorage    storage   
File Size727KB,85 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Download Datasheet Parametric View All

UPD45128841G5-A75-9JF Overview

Synchronous DRAM, 16MX8, 5.4ns, MOS, PDSO54, PLASTIC, TSOP2-54

UPD45128841G5-A75-9JF Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeTSOP2
package instructionTSOP2, TSOP54,.46,32
Contacts54
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time5.4 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
interleaved burst length1,2,4,8
JESD-30 codeR-PDSO-G54
JESD-609 codee0
length22.22 mm
memory density134217728 bit
Memory IC TypeSYNCHRONOUS DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals54
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Encapsulate equivalent codeTSOP54,.46,32
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
refresh cycle4096
Maximum seat height1.2 mm
self refreshYES
Continuous burst length1,2,4,8,FP
Maximum standby current0.001 A
Maximum slew rate0.24 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD45128441, 45128841
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The
μ
PD45128441, 45128841 are high-speed 134,217,728-bit synchronous dynamic random-access memories,
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
EO
Features
Pulsed interface
• ×4, ×8
organization
organized as 8,388,608
×
4
×
4, 4,194,304
×
8
×
4 (word
×
bit
×
bank), respectively.
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
CBR (Auto) refresh and self refresh
Single 3.3 V
±
0.3 V power supply
4,096 refresh cycles / 64 ms
Automatic precharge and controlled precharge
LVTTL compatible inputs and outputs
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0343N10 (Ver. 1.0)
Date Published February 2003 (K) Japan
URL: http://www.elpida.com
L
od
Pr
This product became EOL in March, 2007.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
t
uc
©Elpida
Memory, Inc. 2003
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