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MACH220-12JC

Description
EE PLD, 12 ns, PQCC68
CategoryProgrammable logic devices    Programmable logic   
File Size160KB,33 Pages
ManufacturerAMD
Websitehttp://www.amd.com
Download Datasheet Parametric View All

MACH220-12JC Overview

EE PLD, 12 ns, PQCC68

MACH220-12JC Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAMD
Parts packaging codeLCC
package instructionQCCJ, LDCC68,1.0SQ
Contacts68
Reach Compliance Codeunknow
Other featuresPAL BLOCKS INTERCONNECTED BY PIA; 8 PAL BLOCKS; BURIED MACROCELLS; 4 EXTERNAL CLOCKS
maximum clock frequency62.5 MHz
In-system programmableNO
JESD-30 codeS-PQCC-J68
JESD-609 codee0
JTAG BSTNO
length24.2062 mm
Dedicated input times4
Number of I/O lines48
Number of macro cells96
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
organize4 DEDICATED INPUTS, 48 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Programmable logic typeEE PLD
propagation delay16 ns
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.2062 mm
FINAL
COM’L: -10/12/15/20
IND: -14/18/24
MACH220-10/12/15/20
High-Density EE CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
68 Pins
96 Macrocells
10 ns t
PD
100 MHz f
CNT
56 Inputs with pull-up resistors
48 Outputs
96 Flip-flops; 4 clock choices
Advanced
Micro
Devices
8 “PAL26V12” blocks with buried macrocells
Pin-compatible with MACH120 and MACH221
GENERAL DESCRIPTION
The MACH220 is a member of AMD’s high-performance
EE CMOS MACH 2 device family. This device has
approximately nine times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
The MACH220 consists of eight PAL blocks intercon-
nected by a programmable switch matrix. The eight PAL
blocks are essentially “PAL26V12” structures complete
with product-term arrays, and programmable macro-
cells, including buried macrocells. The switch matrix
connects the PAL blocks to each other and to all input
pins, providing a high degree of connectivity between
the fully-connected PAL blocks. This allows designs to
be placed and routed efficiently.
The MACH220 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the
register can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the
software. All output macrocells can be connected to an
I/O cell. If a buried macrocell is desired, the internal
feedback path from the macrocell can be used, which
frees up the I/O pin for use as an input.
The MACH220 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
Publication#
14130
Rev.
I
Issue Date:
May 1995
Amendment
/0
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