M95640-MB3G/B datasheet, PDF - EEWORLD Datasheet

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M95640-MB3G/B: Description8K X 8 SPI BUS SERIAL EEPROM, PDSO8; Categorystorage storage; File Size721KB，53 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/; Environmental Compliance

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M95640-MB3G/B Overview

8K X 8 SPI BUS SERIAL EEPROM, PDSO8

M95640-MB3G/B Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	STMicroelectronics
Parts packaging code	SOIC
package instruction	2 X 3 MM, ROHS COMPLIANT, MLP-8
Contacts	8
Reach Compliance Code	compli
ECCN code	EAR99
Maximum clock frequency (fCLK)	5 MHz
Data retention time - minimum	40
Durability	1000000 Write/Erase Cycles
JESD-30 code	R-XDSO-N8
length	3 mm
memory density	65536 bi
Memory IC Type	EEPROM
memory width	8
Number of functions	1
Number of terminals	8
word count	8192 words
character code	8000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	8KX8
Package body material	UNSPECIFIED
encapsulated code	VSON
Encapsulate equivalent code	SOLCC8,.11,20
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, VERY THIN PROFILE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	0.6 mm
Serial bus type	SPI
Maximum standby current	0.000005 A
Maximum slew rate	0.004 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	2 mm
Maximum write cycle time (tWC)	5 ms
write protect	HARDWARE/SOFTWARE

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M95640-W M95640-R

M95640-DF

64-Kbit serial SPI bus EEPROM with high-speed clock

Datasheet

production data

Features

•

Compatible with the Serial Peripheral Interface

(SPI) bus

SO8 (MN)

150 mil width

•

Memory array

– 64 Kb (8 Kbytes) of EEPROM

– Page size: 32 bytes

•

Write

– Byte Write within 5 ms

– Page Write within 5 ms

•

Additional Write lockable page (Identification

page)

TSSOP8 (DW)

169 mil width

•

Write Protect: quarter, half or whole memory

array

•

High-speed clock: 20 MHz

•

Single supply voltage:

– 2.5 V to 5.5 V for M95640-W

– 1.8 V to 5.5 V for M95640-R

– 1.7 V to 5.5 V for M95640-DF

•

Operating temperature range: from -40°C up to

+85°C

•

Enhanced ESD protection

•

More than 4 million Write cycles

•

More than 200-year data retention

•

Packages:

– SO8 (ECOPACK2

)

– TSSOP8 (ECOPACK2

)

– UFDFPN8 (ECOPACK2

)

– WLCSP (ECOPACK2

)

UFDFPN8 (MC)

2 x 3 mm

WLCSP (CT)

February 2016

This is information on a product in full production.

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www.st.com

Contents

M95640-W M95640-R M95640-DF

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1

SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1

Supply voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1.1

5.1.2

5.1.3

5.1.4

Operating supply voltage (V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2

5.3

5.4

5.5

Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . 14

Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6.1

6.2

6.3

Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.1

WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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6.3.2

6.3.3

6.3.4

Contents

WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4

6.5

6.6

6.7

6.8

6.9

6.10

Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6.6.1

Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 26

Read Identification Page (available only in M95640-D devices) . . . . . . . 27

Write Identification Page (available only in M95640-D devices) . . . . . . . 28

Read Lock Status (available only in M95640-D devices) . . . . . . . . . . . . . 29

Lock ID (available only in M95640-D devices) . . . . . . . . . . . . . . . . . . . . . 30

Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

7.1

7.2

Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

10.1

10.2

10.3

10.4

SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Thin WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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List of tables

M95640-W M95640-R M95640-DF

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Operating conditions (M95640-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Operating conditions (M95640-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Operating conditions (M95640-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DC characteristics (M95640-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

DC characteristics (M95640-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

DC characteristics (M95640-DF, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

AC characteristics (M95640-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

AC characteristics (M95640-R, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

AC characteristics (M95640-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SO8N – 8-lead plastic small outline, 150 mils body width,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch,

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch

dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale

package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

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List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

8-bump thin WLCSP connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Read Identification Page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Read Lock Status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Lock ID sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 42

SO8N – 8-lead plastic small outline, 150 mils body width,

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

TSSOP8 – 8-lead thin shrink small outline, 3 x 4.4 mm, 0.65 mm pitch,

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch

dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale

package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale

package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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The clock system of STM32 can be directly summarized in a diagram (from the STM32F10X reference manual). The following is an analysis of this diagram 1. STM32 input clock source 1.1 Function of cl...[Details]
Setting problems of multi-channel ADC and DMA of stm32

I have encountered many problems when tinkering with LD driver recently. I will record them one by one below. Otherwise, who will remember who in five hundred years? 1. Configuration issues of multi-...[Details]
52 MCU timer/counter programming summary

/*---------------------------------------------------------------------- TMOD (89H) T1 T0 GATE C/T` M1 M0 GATE C/T` M1 M0 -----------------------...[Details]
LPC1768 external interrupt

/************************************************************************************* * main.c: the main file * NXP -- LPC1768 * * * Author : light *...[Details]
The corresponding relationship between AVR microcontroller registers DDR, PORT and PIN

Each I/O port of the AVR microcontroller corresponds to three registers: DDRx, PORTx and PINx, where DDRx is the data direction, i.e. input or output; PORTx is the state of the internal pull-up r...[Details]
Before changing your home's smart lock, you must first confirm these four points

Pay attention to whether the new lock matches the old door 　　Smart locks have many advantages over traditional mechanical locks. Although the domestic penetration rate is not high, with the strength...[Details]
Integrated experimental board circuit composed of STC12C5412AD single chip

　　The STC12C5412AD microcontroller is an enhanced 8051 standard 51 series microcontroller. It is 12 times faster than the ordinary 8051 and can be programmed on a home computer without an emulator. 　...[Details]
2017, MSO 5 Evolution Trilogy

From early June to November 2017, MSO 5 has been launched with a stunning temperament and appearance. From wider channel selection, more powerful functions, more fashionable touch screen, unprecedent...[Details]
An example of implementing table lookup operation in Samsung S3C/S3P/S3F9XXX series MCU

An example of Samsung S3C/S3P/S3F9XXX series MCU implementing table lookup operation ; to implement table lookup operation, you must first define the table address, there are two ways t...[Details]

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

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