531KA402M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531KA402M000DG

531KA402M000DG: DescriptionCMOS/TTL Output Clock Oscillator, 402MHz Nom, ROHS COMPLIANT, SMD, 6 PIN; CategoryPassive components oscillator; File Size215KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531KA402M000DG Overview

CMOS/TTL Output Clock Oscillator, 402MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531KA402M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	unknown
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	402 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R Y S TA L

S C I L L A T O R

(XO)

(10 M H

Z T O

1.4 G H

)

Features

Available with any-rate output

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz

3rd generation DSPLL

with superior

jitter performance

3x better frequency stability than

SAW-based oscillators

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH

Networking

SD/HD video

Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.1 6/07

Si530/531

Recommended Resources

AC and DC power supply non-stop switching circuit using power supply coupler

HT-6150 circuit-b

Celsius temperature conversion circuit diagram for thermometer

bridge stabilizing link circuit

Amplification circuit and conversion circuit of vortex flowmeter

Bridge motor drive circuit

C2000 Problem Summary Ver 1.0: C28x Based DeviceQ: What is the difference between the TMS320F28xx and the TMS320C28xx MCUs? A: The "F" represents flash, while the "C" represents ROM. The Flash devices are reprogrammable and are ava...; limo Microcontroller MCU

Easy Power Trial Report 4: Summary: I am really sorry for posting so late... I summarized it quite late, and all the experts have already said almost the same thing, and their summary is much better than that of an amateur like me. It i...; winterschs Analogue and Mixed Signal

A BUG found in EE_FPGA V1.0: There are some problems with the connection method of AM29LV160DBBYTE has been grounded by me, so the data width is 8, and only D0-D7 needs to be brought out. In EE_FPGA V1.0, all D0-D15 are brought o...; chenzhufly FPGA/CPLD

Help, OV7725 camera data LCD display has horizontal stripes: The current situation is that the camera output data passes through SDRAM and then is displayed on the LCD. Now there are horizontal stripes on the screen that are rolling in a loop. Because this hori...; deqdqdq FPGA/CPLD

Display failure: When the picture is automatically played under VISTA, it tilts to the right. I don’t know why?: I would like to ask for help with a display failure: Under the VISTA platform, when using the built-in picture player of Windows, the image is biased to the right during automatic playback. This pheno...; yepengju Embedded System

AT91SAM9261EK Development of WINCE 6.0: After installing BSP, I successfully compiled FirstBoot.nb0, Eboot.nb0, nk.bin on vs2005. After downloading them to the board using SAM-BA software, the system cannot boot. Can an expert tell me what ...; zlp520 Embedded System

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components