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© Nexperia B.V. (year). All rights reserved.
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PH5330E
N-channel TrenchMOS logic level FET
Rev. 02 — 19 October 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Higher operating power due to low
thermal resistance
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC convertors
Notebook computers
Portable equipment
Switched-mode power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1
and
3
T
mb
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
30
80
62.5
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 5 V; I
D
= 20 A;
V
DS
= 10 V; T
j
= 25 °C;
see
Figure 11
V
GS
= 10 V; I
D
= 15 A;
T
j
= 25 °C; see
Figure 9
and
10
-
6
-
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
4.8
5.7
mΩ
NXP Semiconductors
PH5330E
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
S
S
S
G
D
Pinning information
Symbol
Description
source
source
source
gate
mounting base; connected to
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
1 2 3 4
SOT669 (LFPAK)
3. Ordering information
Table 3.
Ordering information
Package
Name
PH5330E
LFPAK
Description
plastic single-ended surface-mounted package (LFPAK); 4 leads
Version
SOT669
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 36.2 A;
V
sup
≤
30 V; unclamped; t
p
= 0.15 ms
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
and
3
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
Min
-
-20
-
-
-
-
-55
-55
-
-
-
Max
30
20
50.8
80
250
62.5
150
150
52
208
130
Unit
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
PH5330E_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 19 October 2009
2 of 12
NXP Semiconductors
PH5330E
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03aa23
120
P
der
(%)
80
03aa15
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
10
3
003aaa477
I
D
(A)
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
= 10
μ
s
100
μ
s
1 ms
10 ms
10
DC
100 ms
1
10
−1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PH5330E_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 19 October 2009
3 of 12
NXP Semiconductors
PH5330E
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
2
Unit
K/W
thermal resistance from junction to see
Figure 4
mounting base
10
003aaa478
Z
th(j-mb)
(K/W)
δ
= 0.5
1
0.2
0.1
P
δ
=
t
p
T
single pulse
0.02 0.05
t
p
t
T
10
−1
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PH5330E_2
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 19 October 2009
4 of 12
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