INTEGRATED CIRCUITS
DATA SHEET
TZA3004HL
SDH/SONET data and clock
recovery unit STM1/4 OC3/12
Product specification
Supersedes data of 1998 Feb 09
File under Integrated Circuits, IC19
2000 Nov 28
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
FEATURES
•
Data and clock recovery up to 622 Mbits/s
•
Multi-rate configurable (155 and 622 Mbits/s)
•
Differential data input with 2.5 mV (p-p) typical
sensitivity
•
Differential Current-Mode Logic (CML) data and clock
outputs with 50
Ω
driving capability
•
Adjustable CML output level
•
Loop mode for system testing
•
Bit error rate related loss of signal detection
•
Few external components needed
•
Single supply voltage
•
Power dissipation 370 mW (typical value)
•
LQFP48 plastic package.
ORDERING INFORMATION
TYPE
NUMBER
TZA3004HL
PACKAGE
NAME
LQFP48
DESCRIPTION
APPLICATIONS
TZA3004HL
•
Data and clock recovery in STM1/OC3 and STM4/OC12
transmission systems.
DESCRIPTION
The TZA3004HL is a data and clock recovery IC intended
for use in Synchronous Digital Hierarchy (SDH) and
Synchronous Optical Network (SONET) systems. The
circuit recovers data and extracts the clock signal from an
incoming bitstream up to 622 Mbits/s. It can be configured
for use in STM1/OC3 and STM4/OC12 systems.
VERSION
SOT313-2
plastic low profile quad flat package; 48 leads; body 7
×
7
×
1.4 mm
2000 Nov 28
2
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
BLOCK DIAGRAM
TZA3004HL
handbook, full pagewidth
LOS
39
SEL155
30
FREQUENCY
DIVIDER 1
4/16
AREF
48
ENL
1
42
43
45
DATA
AND
CLOCK
OUTPUT
46
6
7
3
4
DOUT
DOUTQ
COUT
COUTQ
DLOOP
DLOOPQ
CLOOP
CLOOPQ
33
DIN
34
DINQ
ALEXANDER
PHASE
DETECTOR
TZA3004HL
enable
21
22
FREQUENCY
WINDOW
DETECTOR
(1000 ppm)
CREF
CREFQ
+
∫
dt
130 pF
proportional
path
VCRO
integrating
path
130 pF
POWER
CONTROL
37
PC
17
2, 5, 8, 10, 11, 14, 17,
20, 23, 26, 29, 32, 35,
38, 41, 44, 47
FREQUENCY
DIVIDER 2
64/128
12
LOCK
9
24
16
CAPDOQ
CAPUPQ
15
25
VEE1
4
27
28
31
MGU255
GND
DREF19 DREF39
VEE3
VEE2
VEE4
Fig.1 Block diagram.
2000 Nov 28
3
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
PINNING
SYMBOL
ENL
GND
CLOOP
CLOOPQ
GND
DLOOP
DLOOPQ
GND
DREF19
GND
GND
LOCK
i.c.
GND
CAPUPQ
CAPDOQ
GND
i.c.
i.c.
GND
CREF
CREFQ
GND
DREF39
V
EE1
GND
V
EE2
V
EE3
GND
SEL155
V
EE4
GND
DIN
DINQ
GND
i.c.
PC
GND
LOS
i.c.
2000 Nov 28
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
loop mode enable input (active LOW)
ground; note 1
clock output in loop mode (differential)
inverted clock output in loop mode (differential)
ground; note 1
data output in loop mode (differential)
inverted data output in loop mode (differential)
ground; note 1
reference frequency select input 1 (see Table 3)
ground; note 1
ground; note 1
phase lock detection output
internally connected; note 2
ground; note 1
external loop filter capacitor connection
external loop filter capacitor return connection
ground; note 1
internally connected; note 2
internally connected; note 2
ground; note 1
reference clock input (differential)
inverting reference clock input (differential)
ground; note 1
reference frequency select input 2 (see Table 3)
negative supply voltage (−3.3 V); note 3
ground; note 1
negative supply voltage (−3.3 V); note 3
negative supply voltage (−3.3 V); note 3
ground; note 1
STM mode select input 3 (see Table 2)
negative supply voltage (−3.3 V); note 3
ground; note 1
data input (differential)
inverting data input (differential)
ground; note 1
internally connected; note 2
control output for negative power supply
ground; note 1
loss of signal detection output
internally connected; note 2
4
DESCRIPTION
TZA3004HL
Philips Semiconductors
Product specification
SDH/SONET data and clock recovery unit
STM1/4 OC3/12
SYMBOL
GND
DOUT
DOUTQ
GND
COUT
COUTQ
GND
AREF
Notes
1.
ALL
GND pins must be connected;
do not leave one single GND pin unconnected.
PIN
41
42
43
44
45
46
47
48
ground; note 1
data output in normal mode (differential)
inverted data output in normal mode (differential)
ground; note 1
clock output in normal mode (differential)
inverted clock output in normal mode (differential)
ground; note 1
DESCRIPTION
TZA3004HL
reference voltage input for controlling voltage swing on data and clock outputs
2.
ALL
pins denoted ‘i.c.’ have internal connections; external connections to these pins should not be made.
3.
ALL
V
EE
pins must be connected;
do not leave one single V
EE
pin unconnected.
46 COUTQ
45 COUT
42 DOUT
48 AREF
handbook, full pagewidth
43 DOUTQ
38 GND
41 GND
44 GND
47 GND
39 LOS
37 PC
40 i.c.
ENL
1
36 i.c.
35 GND
34 DINQ
33 DIN
32 GND
GND 2
CLOOP 3
CLOOPQ 4
GND 5
DLOOP 6
DLOOPQ 7
GND 8
DREF19 9
GND 10
GND 11
LOCK 12
TZA3004HL
31 VEE4
30 SEL155
29 GND
28 VEE3
27 VEE2
26 GND
25 VEE1
DREF39 24
CREF 21
CAPUPQ 15
CAPDOQ 16
CREFQ 22
i.c. 13
GND 14
GND 17
i.c. 18
i.c. 19
GND 20
GND 23
MGU254
Fig.2 Pin configuration.
2000 Nov 28
5
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