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74ACT11593
8 BIT BINARY COUNTER
WITH PARALLEL INPUT REGISTERS AND 3 STATE OUTPUTS
•
•
•
•
•
•
•
•
Inputs Are TTL-Voltage Compatible
Parallel Register Inputs/Binary
Counter/3-State Outputs
Counter Has Direct Overriding Load and
Clear
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at 125°C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
DW OR NT PACKAGE
(TOP VIEW)
SCAS203 − JUNE 1992 − REVISED APRIL 1993
A/Q
A
B/Q
B
C/Q
C
D/Q
D
GND
GND
GND
GND
E/Q
E
F/Q
F
G/Q
G
H/Q
H
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CCK
CCLR
CCKEN
CCKEN
CLOAD
V
CC
V
CC
OE
OE
RCK
RCK
RCO
description
The 74ACT11593 contains eight multiplexed parallel I/Os with 3-state output capability and an 8-bit storage
register that feeds an 8-bit binary counter. Both the register and the counter have individual positive-edge
triggered clocks.
The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable
(OE, OE) inputs.
The counter input has direct load and clear functions. A low-going RCO pulse is obtained when the counter
reaches the hex word FF.
Expansion is easily accomplished for two stages by connecting RCO of the first stage to CCKEN of the second
stage. Cascading for larger count chains is accomplished by connecting RCO of each stage to CCK of the
following stage.
The 74ACT11593 is characterized for operation from − 40°C to 85°C.
Function Tables
COUNTER CLOCK ENABLE
INPUTS
CCKEN
L
L
H
H
CCKEN
L
H
L
H
OUTPUTS
A/QA THRU H/QH
Disable
Disable
Enable
Disable
OE
L
L
H
H
OUTPUT ENABLE
INPUTS
OE
L
H
L
H
OUTPUTS
A/QA THRU H/QH
Input mode
Input mode
Output mode
Input mode
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
•
2−1
SCAS203 − JUNE 1992 − REVISED APRIL 1993
74ACT11593
8 BIT BINARY COUNTER
WITH PARALLEL INPUT REGISTERS AND 3 STATE OUTPUTS
logic symbol
†
OE
OE
23
CCLR
CCKEN
CCKEN
CCK
CLOAD
RCK
RCK
A/QA
B/QB
C/QC
D/QD
E/QE
F/QF
G/QG
H/QH
2
3
4
9
10
11
12
24
20
14
15
1
4+
C3
G1
1C2
2D
5, 6
3D
22
21
CT = 0
&
G4
CT = 255
13
RCO
17
16
&
EN6
CTR8
Z5
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2−2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
•
74ACT11593
8 BIT BINARY COUNTER
WITH PARALLEL INPUT REGISTERS AND 3 STATE OUTPUTS
SCAS203 − JUNE 1992 − REVISED APRIL 1993
logic diagram (positive logic)
OE
OE
CCLR
17
16
23
CCKEN
CCKEN
CCK
CLOAD
RCK
RCK
A/QA
22
21
24
20
14
15
1
1D
C1
S
T
R
13
RCO
B/QB
2
1D
C1
S
T
R
C/QC
3
1D
C1
S
T
R
D/QD
4
1D
C1
S
T
R
E/QE
9
1D
C1
S
T
R
F/QF
10
1D
C1
S
T
R
G/QG
11
1D
C1
S
T
R
H/QH
12
1D
C1
S
T
R
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
•
2−3
SCAS203 − JUNE 1992 − REVISED APRIL 1993
74ACT11593
8 BIT BINARY COUNTER
WITH PARALLEL INPUT REGISTERS AND 3 STATE OUTPUTS
typical operating sequence
OE
OE
CCLR
CLOAD
CCK
CCKEN
CCKEN
RCK
RCK
Output Hex
A/QA through H/QH
00
Input Hex
FC
Output Hex
FC
Output Hex
FD
Output Hex Output Hex Output Hex
FE
FF
00
RCO
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
225 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2−4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001
•
•
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