Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKTA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH32D72AKTA is 33554432 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 18 industry standard 32M x 4 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin
1pin
FEATURES
Max.
Frequency
CLK
Access Time
[component level]
Type name
MH32D72AKTA-75
MH32D72AKTA-10
133MHz
100MHz
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 32M X 4 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
-
Vdd=Vddq=2.5v ±0.2V
144pin
145pin
52pin
53pin
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- data ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-9,11
- SSTL_2 Interf ace
- Module 1bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
184pin
92pin
APPLICATION
Main memory unit for PC, PC server
MIT-DS-0433-0.2
MITSUBISHI ELECTRIC
5.Oct.2001
1
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKTA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
PIN
NAME
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
RESET
VSS
DQ8
DQ9
DQS1
VDDQ
NC
NC
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
PIN
NO.
43
44
45
46
47
48
49
50
51
52
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDDQ
/WE
DQ41
/CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
NC
NC
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
PIN
NAME
A1
CB0
CB1
VDD
DQS8
A0
CB2
VSS
CB3
BA1
PIN
NO.
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
PIN
NAME
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
VSS
DQ4
DQ5
VDDQ
DQS9
DQ6
DQ7
VSS
NC
NC
A13
VDDQ
DQ12
DQ13
DQS10
VDD
DQ14
DQ15
NC
VDDQ
NC
DQ20
A12
VSS
DQ21
A11
DQS11
VDD
DQ22
A8
DQ23
VSS
A6
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
PIN
NO.
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
KEY
VSS
DQ36
DQ37
VDD
DQS13
DQ38
DQ39
VSS
DQ44
/RAS
DQ45
VDDQ
/S0
NC
DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
PIN
NAME
DQ28
DQ29
VDDQ
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
/CK0
VSS
DQS17
A10
CB6
VDDQ
CB7
NC: Not Connected
PIN
NO.
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
PIN
NAME
NC
VDD
DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
MIT-DS-0433-0.2
MITSUBISHI ELECTRIC
5.Oct.2001
2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKTA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
VSS
/RS0
DQS0
DQ0
DQ1
DQ2
DQ3
DQS
/S
D0
DM
DQS9
DQ4
DQ5
DQ6
DQ7
DQS
/S
D9
DM
DQS1
DQ8
DQ9
DQ10
DQ11
DQS
/S
D1
DM
DQS10
DQ12
DQ13
DQ14
DQ15
DQS
/S
D10
DM
DQS2
DQ16
DQ17
DQ18
DQ19
DQS
/S
D2
DM
DQS11
DQ20
DQ21
DQ22
DQ23
DQS
/S
D11
DM
DQS3
DQ24
DQ25
DQ26
DQ27
DQS
/S
D3
DM
DQS12
DQ28
DQ29
DQ30
DQ31
DQS
/S
D12
DM
VDD
VREF
D0 to D17
D0 to D17
D0 to D17
DQS4
DQ32
DQ33
DQ34
DQ35
DQS
D4
/S
DM
DQS13
DQ36
DQ37
DQ38
DQ39
DQS
/S
D13
DM
VSS
V
DDID
DQS5
DQ40
DQ41
DQ42
DQ43
DQS
/S
D5
DM
DQS14
DQ44
DQ45
DQ46
DQ47
DQS
/S
D14
SCL
WP
A0 A1
DQS
/S
D15
DM
SA0 SA1
A2
SA2
DM
SERIAL PD
SDA
DQS6
DQ48
DQ49
DQ50
DQ51
DQS
D6
/S
DM
DQS15
DQ52
DQ53
DQ54
DQ55
DQS7
DQ56
DQ57
DQ58
DQ59
DQS
/S
D7
DM
DQS16
DQ60
DQ61
DQ62
DQ63
DQS
/S
D16
DM
/S0
BA0-BA1
A0-A11
/RAS
/CAS
CKE0
/WE
PCK
/PCK
/RS0 -> SDRAMs D0-D17
RBA0-RBA1 -> SDRAMs D0-D17
RA0-RA11 -> SDRAMs D0-D17
/RRAS -> SDRAMs D0-D17
/RCAS -> SDRAMs D0-D17
/RCKE0 -> SDRAMs D0-D17
/RWE -> SDRAMs D0-D17
/RESET
DQS8
CB0
CB1
CB2
CB3
DQS
/S
D8
DM
DQS17
CB4
CB5
CB6
CB7
DQS
/S
D17
DM
CK0
/CK0
PCK0 -> SDRAMs D0-D17, Registered Buffer
PLL
/PCK0 -> SDRAMs D0-D17, Registered Buffer
MIT-DS-0433-0.2
MITSUBISHI ELECTRIC
5.Oct.2001
3
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKTA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CK0 and /CK0 are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK0 and negative edge of /CK0. Output (read) data is referenced to
the crossings of CK0 and /CK0 (both directions of crossing).
Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 is low, the
internal clock f or the f ollowing cy c le is ceased. CKE0 is also used to select
auto / self ref resh. After self ref resh mode is started, CKE0 becomes
asy nchronous input. Self ref resh is maintained as long as CKE0 is low.
Phy s ical Bank Select: When /S0 is high, any command means No Operation.
CK0,/CK0
Input
CKE0
Input
/S0
/RAS, /CAS, /WE
Input
Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-11. The Column Address is specif ied by A0-9,11.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.
A0-11
Input
BA0,1
DQ 0-64
CB 0-7
DQS0-17
Vdd, Vss
VddQ, VssQ
Vddspd
Vref
RESET
Input
Input / Output
Input / Output
Power Supply
Power Supply
Power Supply
Input
Input
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write data.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
Power Supply for SPD
SSTL_2 reference voltage.
This signal is asynchronous and is driven low to the register in order to
guarantee the register outputs are low.
This bidirectional pin is used to transf er data into or out of the SPD EEPROM.
A resistor must be connected f rom the SDA bus line to VDD to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected f rom the SCL bus time to VDD to act as a pullup.
These signals are tied at the system planar to either VSS or VDD to conf igure
the serial SPD EEPROM address range.
VDD identif ication f lag
SDA
SCL
SA0-2
VDDID
Input / Output
Input
Input
MIT-DS-0433-0.2
MITSUBISHI ELECTRIC
5.Oct.2001
4
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D72AKTA-10,-75
2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH32D72AKTA provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CK0
CK0
/S0
/RAS
/CAS
/WE
CKE0
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
def ine basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge,
WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all,
PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0433-0.2
5.Oct.2001
MITSUBISHI ELECTRIC
5
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