• CAS before RAS refresh, Hidden refresh capabilities
Early-write mode and OE to control output buffer impedance
• All inputs, output TTL compatible and low capacitance
• 2048 refresh cycles every 32ms (A
0
~ A
10
)
*Applicable to self refresh version (M5M417400CJ,TP-5S,-6S,
-7S :option) only
APPLICATION
Main memory unit for computers, Microcomputer memory, Refresh
memory for CRT
Outline 26P3D-E (300mil TSOP)
NC: NO CONNECTION
1
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
FUNCTION
The M5M417400CJ,TP provide, in addition to normal read, write, and read-modify-write operations, a number of other functions, e.g., fast
page mode, RAS-only refresh, and delayed-write. The input conditions for each are shown in Table 1.
Table 1 Input conditions for each mode
Inputs
Operation
Read
Write (Early write)
Write (Delayed write)
Read-modify-write
RAS-only refresh
Hidden refresh
Self refresh
CAS before RAS refresh
Stand-by
RAS
ACT
ACT
ACT
ACT
ACT
ACT
ACT
ACT
NAC
CAS
ACT
ACT
ACT
ACT
NAC
ACT
ACT
ACT
DNC
W
NAC
ACT
ACT
ACT
DNC
NAC
NAC
NAC
DNC
OE
ACT
DNC
DNC
ACT
DNC
ACT
DNC
DNC
DNC
Row
address
APD
APD
APD
APD
APD
APD
DNC
DNC
DNC
Column
address
APD
APD
APD
APD
DNC
DNC
DNC
DNC
DNC
Input/Output
Input
OPN
VLD
VLD
VLD
DNC
OPN
DNC
DNC
DNC
Output
VLD
OPN
IVD
VLD
OPN
VLD
OPN
OPN
OPN
Refresh
YES
YES
YES
YES
YES
YES
YES
YES
NO
Remark
Fast
page
mode
identical
Note: ACT: active, NAC: nonactive, DNC: don’t care, VLD: valid, IVD: invalid, APD: applied, OPN: open
BLOCK DIAGRAM
2
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
O
P
d
T
opr
T
stg
Supply voltage
Input voltage
Output voltage
Output current
Power dissipation
Operating temperature
Storage temperature
Ta = 25°C
With respect to V
SS
Parameter
Conditions
Ratings
-1 ~ 7
-1 ~ 7
-1 ~ 7
50
1000
0 ~ 70
-65 ~ 150
Unit
V
V
V
mA
mW
°C
°C
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 ~ 70°C, unless otherwise noted) (Note 1)
Symbol
V
CC
V
SS
V
IH
V
IL
Note 1:
Supply voltage
Supply voltage
High-level input voltage, all inputs
Low-level input voltage, all inputs
All voltage values are with respect to V
SS
.
Parameter
Limits
Min
4.5
0
2.4
-1.0**
Nom
5
0
Max
5.5
0
5.5
0.8
Unit
V
V
V
V
**: V
IL(min.)
is -2.0V when undershoot width is less than 25ns. (Undershoot width is with respect to V
SS
.)
ELECTRICAL CHARACTERISTICS
(Ta = 0 ~ 70°C, V
CC
= 5V ± 10%, V
SS
= 0V, unless otherwise noted) (Note 2)
Symbol
V
OH
V
OL
l
OZ
I
I
I
CC1(AV)
High-level output voltage
Low-level output voltage
Off-state output current
Input current
Average supply current
from V
CC
, operating
(Note 3,4)
I
CC2
Supply current from V
CC
, stand-by
Average supply current
I
CC3 (AV)
from V
CC
, refreshing
(Note 3)
Average supply current
I
CC4 (AV)
from V
CC
, Fast-Page-Mode
(Note 3,4)
Average supply current from V
CC
,
I
CC6 (AV)
CAS before RAS refresh mode
(Note 3)
Note 2:
3:
4:
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
(Note 5)
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
M5M417400C-5,-5S
M5M417400C-6,-6S
M5M417400C-7,-7S
Parameter
I
OH
= -5.0mA
I
OL
= 4.2mA
Q floating 0V
≤
V
OUT
≤
5.5V
0V
≤
V
IN
≤5.5V,
Other inputs pins = 0V
RAS, CAS cycling
t
RC
= t
WC
= min.
output open
RAS = CAS = V
IH
, output open
RAS = CAS
≥
V
CC
-0.2V
RAS cycling, CAS = V
IH
t
RC
= min.
output open
RAS = V
IL
, CAS cycling
t
PC
= min.
output open
CAS before RAS refresh cycling
t
RC
= min.
output open
Test conditions
Limits
Min
2.4
0
-10
-10
Typ
Max
V
CC
0.4
10
10
145
120
105
2
0.5
145
120
105
80
70
60
145
120
105
mA
mA
mA
mA
mA
Unit
V
V
µA
µA
Current flowing into an IC is positive, out is negative.
I
CC1
(AV), I
CC3
(AV), I
CC4
(AV) and I
CC6
(AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
I
CC1
(AV) and I
CC4
(AV) are dependent on output loading. Specified values are obtained with the output open.
3
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
CAPACITANCE
(Ta = 0 ~ 70°C, V
CC
= 5V ± 10%, V
SS
= 0V, unless otherwise noted)
Symbol
C
I(A)
C
I(OE)
C
I(W)
C
I(RAS)
C
I(CAS)
C
I/O
Parameter
Input capacitance, address inputs
Input capacitance, OE input
Input capacitance, write control input
Input capacitance, RAS input
Input capacitance, CAS input
Input/Output capacitance, data ports
V
I
= V
SS
f = 1MHz
V
I
= 25mVrms
Test conditions
Limits
Min
Typ
Max
5
7
7
7
7
8
Unit
pF
pF
pF
pF
pF
pF
SWITCHING CHARACTERISTICS
(Ta = 0 ~ 70°C, V
CC
= 5V ± 10%, V
SS
= 0V, unless otherwise noted, see notes 5, 12, 13)
Limits
Symbol
Parameter
M5M417400C-5,-5S
Min
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
CLZ
t
OFF
t
OEZ
Note 5:
Access time from CAS
Access time from RAS
Column address access time
Access time from CAS precharge
Access time from OE
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high
(Note 6, 7)
(Note 6, 8)
(Note 6, 9)
(Note 6, 10)
(Note 6)
(Note 6)
(Note 11)
(Note 11)
5
0
0
13
13
Max
13
50
25
30
13
5
0
0
15
15
M5M417400C-6,-6S
Min
Max
15
60
30
35
15
5
0
0
15
15
M5M417400C-7,-7S
Min
Max
20
70
35
40
20
ns
ns
ns
ns
ns
ns
ns
ns
Unit
An initial pause of 500
µ
s is required after power-up followed by a minimum of eight initialization RAS cycles. The initialization cycles should be done either by RAS-only
refresh cycles or by CAS before RAS refresh cycles only.
Note the RAS may be cycled during the initial pause. And any 8 RAS or RAS/CAS cycles are required after prolonged periods (greater than 32ms) of RAS inactivity before
proper device operation is achieved.
After the initialization cycles, RAS should be kept either higher than V
IH(min)
or lower than V
IL(max)
except RAS transition time.
Measured with a load circuit equivalent to 2 TTL loads and 100pF.
Assumes that t
RCD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max)
.
Assumes that t
RCD
≤
t
RCD(max)
and t
RAD
≤
t
RAD(max)
. If t
RCD
or t
RAD
is greater than the maximum recommended value shown in this table, t
RAC
will increase by amount that
t
RCD
exceeds the value shown.
Assumes that t
RAD
≥
t
RAD(max)
and t
ASC
≤
t
ASC(max)
.
Assumes that t
CP
≤
t
CP(max)
and t
ASC
≥
t
ASC(max)
.
t
OFF(max)
and t
OEZ(max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
| ± 10
µA
|) and is not reference to V
OH(min)
or V
OL(max)
.
6:
7:
8:
9:
10:
11:
4
MITSUBISHI LSIs
M5M417400CJ,TP-5,-6,-7,-5S,-6S,-7S
FAST PAGE MODE 16777216-BIT (4194304-WORD BY 4-BIT) DYNAMIC RAM
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