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ST1500ECBK-FREQ3

Description
HCMOS/TTL Output Clock Oscillator, 70MHz Min, 100MHz Max,
CategoryPassive components    oscillator   
File Size5MB,4 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric View All

ST1500ECBK-FREQ3 Overview

HCMOS/TTL Output Clock Oscillator, 70MHz Min, 100MHz Max,

ST1500ECBK-FREQ3 Parametric

Parameter NameAttribute value
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresTRI-STATE; BULK
Maximum control voltage4.5 V
Minimum control voltage0.5 V
maximum descent time3 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate200 ppm
frequency stability50%
linearity10%
Manufacturer's serial numberS1500
Installation featuresSURFACE MOUNT
Maximum operating frequency100 MHz
Minimum operating frequency70 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeHCMOS/TTL
Output load15 pF
longest rise time3 ns
Maximum supply voltage5.5 V
Minimum supply voltage4.5 V
Nominal supply voltage5 V
surface mountYES
maximum symmetry40/60 %
Base Number Matches1
SaRonix
Voltage Controlled Crystal Oscillator
Technical Data
Frequency Range:
Frequency Stability:
5V, HCMOS
S150x / ST150x Series
1.5 MHz to 100 MHz ( Full Size )
1.5 MHz to 28.6363 MHz ( Half Size )
±20, ±25 or ±50 ppm over all conditions: operating
temperature, voltage change, load change, calibration
tolerance, shock and vibration, with V
C
= 2.5V
± 3ppm max per year, ±10ppm max for 10 years
Aging @ 25°C:
Temperature Range:
Operating:
Storage:
Supply Voltage:
Recommended Operating:
ACTUAL SIZE
0 to +70°C or -40 to +85°C
-55 to +125°C
5V ±10%
Description
A voltage controlled crystal oscillator
designed with excellent Jitter character-
istics - ideal for telecom applications.
The HCMOS output can drive high speed
CMOS & TTL loads. Devices are in
standard 14-pin DIP metal packages. Pin
7(4 on 1/2 size) is grounded to reduce
EMI. SMD DIL 14 version is available
utilizing adaptor technology (see sepa-
rate data sheet for dimensions).
Applications & Features
Phase Locked Loop (PLL) Clock &
Data Recovery, Frequency Translation,
Frequency Synthesis in Video, Video
Compression, Telephony, and LAN/
WAN Data Communication and other
Telecommunication applications.
HCMOS / TTL compatible
3.5ps max RMS period jitter
± 50, 100 or 200 ppm APR*
± 20, 25 or 50 ppm Stability
Tri-State option available
SMD versions for IR reflow available
Output Waveform
CMOS
T
r
Logic 1
80%V
DD
50%V
DD
20%V
DD
Logic 0
T
f
Supply Current:
Full Size Package:
Half Size Package:
Output Drive:
Symmetry:
Rise & Fall Times:
1.5 to 25 MHz:
25+ to 70 MHz:
70+ to 100 MHz:
1.5 to 28.6363 MHz:
Logic 0:
Logic 1:
Load:
Period Jitter RMS:
Pull Characteristics:
Input Impedance (pin 1):
Frequency Response (-3dB):
Pullability:
Control Voltage:
Transfer Function:
Linearity:
Center Control Voltage:
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Solvent Resistance:
Resistance to Soldering Heat:
Environmental:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Moisture Resistance:
1.5 to 11.9MHz:
12 to 70MHz:
70+ to 100MHz:
1.5 to 28.6363MHz:
20mA
65mA
60mA
25mA
max
max
max
max
with
with
with
with
30pF
30pF
15pF
30pF
load
load
load
load
45/55% max @ 50% V
DD
1.5 to 70 MHz
40/60% max @ 50% V
DD
70+ to 100 MHz
20% to 80% V
DD
8ns max rise, 6ns max fall, full size package
5ns max rise & fall, full size package
3ns max rise & fall, full size package
6ns max rise & fall, half size package
10% V
DD
max
90% V
DD
min
30pF to 70 MHz, 15pF from 70+ to 100 MHz
3.5ps max
50KΩ min
10 kHz min
±50, ±100, ±200ppm APR* min, See Part Numbering Guide
0.5 to 4.5V
Frequency increases when Control Voltage increases
5 or 10% max
2.5V
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-883, Method 2004, Conditions B2
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 215
MIL-STD-202, Method 210, Conditions A, B or C
( I or J for Gull Wing or SMD)
MIL-STD-883C,
MIL-STD-883C,
MIL-STD-883C,
MIL-STD-883C,
Method
Method
Method
Method
1014, Condition C
1014, Condition A2
1011, Condition A
1004
*
APR = (VCXO Pull relative to specified Output Frequency)
(VCXO Frequency Stability) – (Aging)
SYMMETRY
10 years aging is inclusive on 1/2 size version
DS-197
REV E
SaRonix
www.pericom.com/saronix
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