256Kx4 High Speed Static RAM(3.3V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.
CMOS SRAM
Revision History
Rev . No.
Rev. 0.0
Rev. 1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary
Release to final Data Sheet.
2.1. Delete Preliminary
Add Low Power Product and update D.C parameters.
3.1. Add Low Power Products with Isb1=0.5mA and Data Retention
Mode(L-ver. only)
3.2. Update D.C parameters
Previous spec.
Updated spec.
Items
(12/15/17/20ns part)
(12/15/17/20ns part)
Icc
160/155/150/145mA
130/125/125/120mA
Isb
30mA
20mA
Isb1
10mA
5mA
Add Industrial Temperature Range parts
4.1. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
4.1.1. Add KM64V1003AI/ALI parts for Industrial Temperature
Range.
4.1.2. Add ordering information.
4.1.3. Add the condition for operating at Industrial Temp. Range.
4.2. Add timing diagram to define t
WP
as
″(Timing
Wave Form of
Write Cycle(CS=Controlled)″
5.1. Delete L-version.
5.2. Delete Data Rentention Characteristics and Wavetorm.
5.3. Delete 17ns Part
5.4. Delete TSOP2 Package
5.5. Delete Industrial Temperature Range Part
5.6. Add Capacitive load of the test environment in A.C test load
Draft Data
Jan. 18th, 1995
Apr. 22th, 1995
Remark
Design Target
Preliminary
Rev. 2.0
Feb. 29th, 1996
Final
Rev. 3.0
Jul. 16th, 1996
Final
Rev. 4.0
Jun. 2nd, 1997
Final
Rev. 5.0
Feb. 25th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
Rev 5.0
February 1998
-1-
PRELIMINARY
KM64V1003A
CMOS SRAM
256K x 4 Bit(with OE) High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating KM64V1003A - 12 : 130mA(Max.)
KM64V1003A - 15 : 125mA(Max.)
KM64V1003A - 20 : 120mA(Max.)
• Single 3.3
±
0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration
KM64V1003AJ : 32-SOJ-400
GENERAL DESCRIPTION
The KM64V1003A is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 262,144 words by 4 bits.
The KM64V1003A uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
KM64V1003A is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION
(Top View)
32 A
17
31 A
16
30 A
15
29 A
14
28 A
13
27
OE
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
~I/O
4
A
0
A
1
A
2
Pre-Charge Circuit
A
3
CS
I/O
1
26 I/O
4
Row Select
Vcc
Memory Array
512 Rows
512x4 Columns
Vss
I/O
2
WE
A
4
A
5
A
6
SOJ/
TSOP2
25 Vss
24 Vcc
23 I/O
3
22 A
12
21 A
11
20 A
10
19
18
A
9
A
8
Data
Cont.
CLK
Gen.
A
9
I/O Circuit &
Column Select
A
7
N.C. 16
17 N.C.
A
10
A
12
A
14
A
16
A
11
A
13
A
15
A
17
PIN FUNCTION
Pin Name
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
A
0
- A
17
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
CS
WE
OE
-2-
Rev 5.0
February 1998
PRELIMINARY
KM64V1003A
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
Unit
V
V
CMOS SRAM
W
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.2
-0.3*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+ 0.3**
0.8
Unit
V
V
V
V
*
V
IL
(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA
**
V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width≤10ns) for I≤20mA
DC AND OPERATING CHARACTERISTICS
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
= V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
Min
-2
-2
-
-
-
-
-
-
2.4
Max
2
2
130
125
120
20
5
0.4
-
mA
mA
V
V
Unit
µA
µA
mA
CAPACITANCE*
( T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
* NOTE : Capacitance is sampled and not 100% tested.
-3-
Rev 5.0
February 1998
PRELIMINARY
KM64V1003A
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
3ns
1.5V
See below
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
353Ω
319Ω
5pF*
* Capacitive Load consists of all components of the
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