Features
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8-bit Resolution
ADC Gain Adjust
1.5 GHz Full Power Input Bandwidth (-3 dB)
1 GSPS (min) Sampling Rate
SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,
at F
S
= 1 GSPS, F
IN
= 20 MHz
SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,
at F
S
= 1 GSPS, F
IN
= 500 MHz
SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,
at F
S
= 1 GSPS, F
IN
= 1000 MHz (-3 dB FS)
2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS
DNL = 0.3 lsb, INL = 0.7 lsb
Low Bit Error Rate (10
-13
) at 1 GSPS
Very Low Input Capacitance: 3 pF
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50Ω ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Power Consumption: 3.4W at Tj = 70°C Typical
Radiation Tolerance Oriented Design (150 Krad (Si) measured)
Two Package Versions
ESA/SCC Detailed Specification Available on Request
Enhanced CQFP68 Packaged Device: TS8388BFS
Evaluation board: TSEV8388BF
Demultiplexer: TS81102G0: Companion Device Available
ADC 8-bit
1 GSPS
TS8388BF
Applications
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Digital Sampling Oscilloscopes
Satellite Receiver
Electronic Countermeasures/Electronic Warfare
Direct RF Down-conversion
Screening
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Atmel Standard Screening Level
Mil-PRF-38535, QML Level Q for Package Version, DSCC 5962-0050401QYC
Temperature Range: up to -55°C < Tc; Tj < +125°C
Description
The TS8388BF is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.
The TS8388BF uses an innovative architecture,
including an on-chip Sample and Hold (S/H),
and is fabricated with an advanced
high speed bipolar process.
The on-chip S/H has a 1.5 GHz full power
input bandwidth, providing excellent dynamic
performance in undersampling applications
(High IF digitizing).
F Suffix: CQFP 68
Ceramic Quad Flat Pack
Rev. 2144A–BDC–04/02
1
Functional
Description
Block Diagram
The following figure shows the simplified block diagram.
Figure 1.
Simplified Block Diagram
GAIN
MASTER/SLAVE TRACK & HOLD AMPLIFIER
V
IN
, V
INB
G=2
T/H
G=1
T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
4
INTERPOLATION
STAGES
4
5
REGENERATION
LATCHES
4
5
ERROR CORRECTION &
DECODE LOGIC
CLOCK
BUFFER
8
OUTPUT LATCHES &
BUFFERS
8
DRRB DR, DRB
GORB
DATA, DATAB OR, ORB
CLK, CLKB
Functional
Description
The TS8388BF is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology
featuring a cutoff frequency of 25 GHz.
The TS8388BF includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering
an error correction circuitry and a resynchronization stage followed by 75Ω differential output
buffers.
The TS8388BF works in fully differential mode from analog inputs up to digital outputs.
The TS8388BF features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388BF.
The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysil-
icon resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
2
TS8388BF
2144A–BDC–04/02
TS8388BF
Specifications
Absolute
Maximum Ratings
Table 1.
Absolute Maximum Ratings
Parameter
Positive supply voltage
Digital negative supply voltage
Digital positive supply voltage
Negative supply voltage
Maximum difference between negative supply voltage
Analog input voltages
Maximum difference between V
IN
and V
INB
Digital input voltage
Digital input voltage
Digital output voltage
Clock input voltage
Maximum difference between V
CLK
and V
CLKB
Maximum junction temperature
Storage temperature
Lead temperature (soldering 10s)
Note:
Symbol
V
CC
DV
EE
V
PLUSD
V
EE
DV
EE
to V
EE
V
IN
or V
INB
V
IN
- V
INB
V
D
V
D
V
O
V
CLK
or V
CLKB
V
CLK
- V
CLKB
T
j
T
stg
T
leads
GORB
DRRB
Comments
Value
GND to 6
GND to -5.7
GND -0.3 to 2.8
GND to -6
0.3
-1 to +1
-2 to +2
-0.3 to V
CC
+0.3
V
EE
-0.3 to +0.9
V
PLUSD
-3 to V
PLUSD
-0.5
-3 to +1.5
-2 to +2
+135
-65 to +150
+300
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat
sink is mandatory. See “The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package installed.” on
page 37.
Recommended
Operating
Conditions
Table 2.
Recommended Operating Conditions
Recommended Value
Parameter
Positive supply voltage
Positive digital supply voltage
Positive digital supply voltage
Negative supply voltage
Symbol
V
CC
V
PLUSD
V
PLUSD
V
EE,
DV
EE
ECL output compatibility
LVDS output compatibility
Comments
Min
4.5
–
+1.4
-5.25
Typ
+5
GND
+2.4
-5
Max
5.25
–
+2.6
-4.75
Unit
V
V
V
V
3
2144A–BDC–04/02
Table 2.
Recommended Operating Conditions (Continued)
Recommended Value
Parameter
Differential analog input voltage
(Full Scale)
Clock input power level
Operating temperature range
Symbol
V
IN,
V
INB
V
IN
- V
INB
P
CLK,
P
CLKB
T
J
Comments
50Ω differential or single-ended
50Ω single-ended clock input
Commercial grade: “C”
Industrial grade: “V”
Military grade: “M”
Min
±113
450
3
Typ
±125
500
4
0 < Tc; Tj < 90
-40 < Tc; Tj < 110
-55 < Tc; Tj < +125
Max
±137
550
10
Unit
mV
mVpp
dBm
°C
Electrical
Operating
Characteristics
V
EE
= DV
EE
= -5V; V
CC
= +5V; V
IN
-V
INB
= 500 mVpp Full Scale differential input;
Digital outputs 75 or 50Ω differentially terminated;
Tj (typical) = 70°C. Full Temperature Range: up to -55°C < Tc; Tj < +125°C.
Table 3.
Electrical Specifications
Test
Level
Value
Min
Typ
Max
Unit
Note
Parameter
Power Requirements
Positive supply voltage
Analog
Digital (ECL)
Digital (LVDS)
Positive supply current
Analog
Digital
Negative supply voltage
Negative supply current
Analog
Digital
Nominal power dissipation
Power supply rejection ratio
Resolution
Symbol
V
CC
V
PLUSD
V
PLUSD
I
CC
I
PLUSD
V
EE
AI
EE
DI
EE
1, 2, 6
4
4
1, 2
6
1, 2
6
1, 2, 6
1, 2
6
1, 2
6
1, 2
6
4
–
4.7
–
1.4
–
–
–
–
-5.3
–
–
–
–
–
–
–
–
5
0
2.4
385
395
115
120
-5
165
170
135
145
3.4
3.6
0.5
8
5.3
–
2.6
445
445
145
145
-4.7
200
200
180
180
4.1
4.3
2
–
V
V
V
mA
mA
mA
mA
V
mA
mA
mA
mA
W
W
mW
bits
(2)
PD
PSRR
–
4
TS8388BF
2144A–BDC–04/02
TS8388BF
Table 3.
Electrical Specifications (Continued)
Test
Level
Value
Min
Typ
Max
Unit
Note
Parameter
Analog Inputs
Full Scale Input Voltage range (differential mode)
(0V common mode voltage)
Full Scale Input Voltage range (single-ended input
option) (See Application Notes)
Analog input capacitance
Input bias current
Input Resistance
Full Power input Bandwidth
Small signal input Bandwidth (10% full scale)
Clock Inputs
Logic compatibility for clock inputs
(See Application Notes)
ECL Clock inputs voltages (V
CLK
or V
CLKB
):
Logic “0” voltage
Logic “1” voltage
Logic “0” current
Logic “1” current
Clock input power level into 50Ω termination
Clock input power level
Clock input capacitance
Symbol
V
IN
V
INB
V
IN
V
INB
C
IN
I
IN
R
IN
FPBW
SSBW
4
–
4
–
4
4
4
4
4
-125
-125
-250
–
–
–
0.5
1.3
1.5
–
–
–
0
3
10
1
1.5
1.7
125
125
250
–
3.5
20
–
–
–
mV
mV
mV
mV
pF
µA
MΩ
GHz
GHz
–
–
V
IL
V
IH
I
IL
I
IH
–
–
C
CLK
–
4
–
–
–
–
–
4
4
ECL or specified clock input
power level in dBm
–
–
-1.1
–
–
–
–
–
5
5
dBm into 50Ω
-2
–
4
3
10
3.5
–
-1.5
–
50
50
–
–
V
V
µA
µA
–
dBm
pF
(10)
Digital Outputs
Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,
Tj (typical) = 70
°
C.
Logic compatibility for digital outputs
(Depending on the value of V
PLUSD
)
(See Application Notes)
Differential output voltage swings
(assuming V
PLUSD
= 0V):
75Ω open transmission lines (ECL levels)
75Ω differentially terminated
50Ω differentially terminated
Output levels (assuming V
PLUSD
= 0V)
75Ω open transmission lines:
Logic “0” voltage
Logic “1” voltage
–
–
ECL or LVDS
–
(1)(6)
–
–
–
–
–
V
OL
V
OH
4
–
–
–
4
–
–
–
1.5
0.70
0.54
–
–
-0.88
–
1.620
0.825
0.660
–
-1.62
-0.8
–
–
–
–
–
-1.54
–
–
V
V
V
–
V
V
(6)
5
2144A–BDC–04/02
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