EEWORLDEEWORLDEEWORLD

Part Number

Search

M3H73FCG

Description
8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
File Size224KB,1 Pages
ManufacturerMtronPTI
Websitehttp://www.mtronpti.com
Download Datasheet View All

M3H73FCG Overview

8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator

M3H & MH Series
8 pin DIP, 3.3 or 5.0 Volt, HCMOS/TTL Clock Oscillator
3.3 or 5.0 Volt Versions
RoHs Compliant Version available
Low Jitter
Pin Connections
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
1-800-762-8800.
Revision: 11-29-06
Schematic diagram of full-band FM radio
A netizen's full-band FM radio schematic diagram. The circuit is relatively simple, using a frequency synthesis high-frequency head and electronic volume control. It is for your reference. [[i] This p...
RF研究 RF/Wirelessly
[ESP32 Learning_1] The first ESP32-S3 example - hello_world
[i=s]This post was last edited by mars4zhu on 2022-7-16 20:00[/i]The first ESP32-S3 example - hello_worldCompile and runFollowing the step-by-step instructions in the document, execute the following c...
mars4zhu DigiKey Technology Zone
[Xiao Meige FPGA Advanced Tutorial] Chapter 11 Four-channel Amplitude-Frequency-Phase Adjustable DDS Signal Generator
[align=center][color=#000][size=15px][b][size=6]XI. Four-channel DDS signal generator with adjustable amplitude, frequency and phase[/size][/b][/size][/color][/align] [align=center][color=#000][size=1...
芯航线跑堂 FPGA/CPLD
What to do after wince starts and initializes FLASH?
Please tell me, when wince starts, what operations are performed after initializing FLASH? How can I know whether FLASH initialization is successful? Thank you...
xfzhaoyong Embedded System
Xi'an Datang Telecom FPGA/CPLD Design Experience Sharing
Let's learn together and make progress together. . . . [[i] This post was last edited by Heshixifengbeihuashan on 2010-11-22 10:56 [/i]]...
何事西风悲画扇 FPGA/CPLD
EMIF SDRAM Addressing
[size=5][color=#0000ff]EMIF_SDRAM I wrote a question about it before. Now I want to ask how the address of SDRAM is obtained. I know that SDRAM is divided into row address and column address. But I do...
YXQWXN DSP and ARM Processors

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1037  1697  608  1893  2897  21  35  13  39  59 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号