PRELIMINARY SPECIFICATION
PE4230
Product Description
The PE4230 High Power MOSFET RF Switch is
designed to cover a broad range of uses in the 10 MHz
through 2.5 GHz frequency range. This switch integrates
on-board CMOS control logic with a low voltage CMOS
compatible control input. Using nominal power supply
voltages, a 1 dB compression point of +30 dBm can be
achieved.
The PE4230 High Power MOSFET RF Switch is
manufactured in Peregrine’s patented Ultra Thin Silicon
(UTSi
) CMOS process, offering the performance of
GaAs with the economy and integration of conventional
CMOS.
SPDT High Power
MOSFET RF Switch
Features
•
Single 3.0 V Power Supply
•
Low Insertion loss: 0.44 dB at
1.0 GHz, 0.50 dB at 2.0 GHz
•
High isolation of 38 dB at 1.0
GHz, 28 dB at 2.0 GHz
•
Typical 1 dB compression of
+30 dBm
•
Low voltage CMOS logic
control
•
Low Cost
Figure 1. Functional Schematic Diagram
RF1
Figure 2. Package Drawings
3.05
2.85
RFCommon
Control
RF2
8-lead
MSOP
5.05
4.75
Table 1. Electrical Specifications @ +25 °C, V
DD
= 3 V
(Z
S
= Z
L
= 50
Ω)
Parameter
Operation Frequency
Insertion Loss
Isolation
Return Loss
‘ON’ Switching Time
‘OFF’ Switching Time
Full Cycle Switching Time
Video Feedthrough
1
Conditions
Minimum
10
Typical
Maximum
2500
Units
MHz
dB
dB
dB
dB
dB
dB
ns
ns
µs
mV
pp
dBm
dBm
1000 MHz
2000 MHz
1000 MHz
2000 MHz
1000 MHz
2000 MHz
CTRL to 0.1 dB final value, 2 GHz
CTRL to 25 dB isolation, 2 GHz
0.44
0.50
38
28
20
14
200
90
5
15
Input 1 dB Compression
Input IP3
2000 MHz
2000 MHz, 17 dBm
30
50
PEREGRINE SEMICONDUCTOR CORP.
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Copyright
Peregrine Semiconductor Corp. 2001
Page 1 of 6
PE4230
Preliminary Specification
Figure 3. Pin Configuration
V
DD
CTRL
1
2
8
7
RF1
GND
GND
Table 4. DC Electrical Specifications
Parameter
V
DD
Power Supply Voltage
Power Supply Current
Control Voltage High
6
5
Min
2.7
0.7x
V
DD
Typ
3.0
29
Max
3.3
Units
V
µA
V
PE4230
GND
RFCommon
3
4
Control Voltage Low
0.3x
V
DD
V
RF2
Table 5. Control Logic Truth Table
Table 2. Pin Descriptions
Pin No.
1
Control Voltage
Description
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFCommon to RF1
RFCommon to RF2
Pin
Name
V
DD
Nominal 3 V supply connection. A
bypass capacitor (100 pF) to the ground
plane should be placed as close as
possible to the pin
CMOS or TTL logic level:
High = RFCommon to RF1 signal path
Low = RFCommon to RF2 signal path
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Common RF port for switch (Note 1)
RF2 port (Note 1)
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground Connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port (Note 1)
Electrostatic Discharge (ESD) Precautions
When handling this UTSi device, observe the same
precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UTSi CMOS
devices are immune to latch-up.
2
CTRL
3
GND
4
5
6
RF
Common
RF2
GND
7
GND
8
RF1
Note 1:
All RF pins must be DC blocked with an external
series capacitor.
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
V
ESD
Parameter/Conditions
Power supply voltage
Voltage on any input
Storage temperature range
Operating temperature
range
ESD voltage (Human Body
Model)
Min
-0.3
-0.3
-65
-40
200
Max
4.0
V
DD
+
0.3
150
85
Units
V
V
°C
°C
V
Copyright
Peregrine Semiconductor Corp. 2001
File No. 70/0029~06B
|
UTSi
CMOS RFIC SOLUTIONS
Page 2 of 6
PE4230
Preliminary Specification
Typical Performance Data @ +25
°C
Figure 4. Insertion Loss & Isolation
Insertion Loss & Isolation
0
-0.1
-0.2
-0.3
Insertion Loss (dB)
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
0
500
1000
1500
2000
2500
Insertion Loss (dB)
Isolation (dB)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
3000
25
20
0
500
1000
1500
2000
2500
1dB Compression Point (dBm)
25
20
3000
Isolation (dB)
1dB Compression Point (dBm)
50
45
40
35
30
50
45
IP3 (dBM)
40
35
30
60
55
IP3 (dBM)
Figure 5. 1 dB Compression Point & IP3
1dB Compression Point & IP3
60
55
Frequency (MHz)
Frequency (MHz)
Figure 6. Switching Time
Figure 7. Video Feedthrough*
CTRL
CTRL
RF1
RF2
*The DC transient at the output of any port of the switch when the
control voltage is switched from Low to High or High to Low in a 50
ohm test set-up, measured with 1ns risetime pulses and 500 MHz
bandwidth.
PEREGRINE SEMICONDUCTOR CORP.
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http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 3 of 6
PE4230
Preliminary Specification
Figure 8. Package Drawing
8-lead MSOP
TOP VIEW
0.65BSC
8
7
6
5
.525BSC
2.45±0.10
2X
3.00±0.10
0.51±0.13
-B-
1
2
3
4
.25 A B C
0.51±0.13
2.95±0.10
-C-
0.86±0.08
2.95±0.10
1.10 MAX
-A-
0.10 A
0.33+0.07
-0.08
0.08
A B C
3.00±0.10
FRONT VIEW
SIDE VIEW
0.10±0.05
3.00±0.10
4.90±0.15
Copyright
Peregrine Semiconductor Corp. 2001
File No. 70/0029~06B
|
UTSi
CMOS RFIC SOLUTIONS
Page 4 of 6
PE4230
Preliminary Specification
Table 6. Ordering Information
Order
Code
4230-21
4230-22
4230-00
Part Marking
4230
4230
PE4230-EK
Description
Package
8-lead MSOP
8-lead MSOP
Evaluation Kit
Shipping
Method
50 pcs. / Tube
2000 pcs. / T&R
1 / Box
PEREGRINE SEMICONDUCTOR CORP.
|
http://www.peregrine-semi.com
Copyright
Peregrine Semiconductor Corp. 2001
Page 5 of 6
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