Dat a Sh eet, V1. 0, A pr. 2008
TC1163/TC1164
32-Bit Single-Chip Microcontroller
TriCore
Microcontrollers
Edition 2008-04
Published by
Infineon Technologies AG
81726 München, Germany
©
Infineon Technologies AG 2008.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-
infringement of intellectual property rights of any third party.
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Dat a Sh eet, V1. 0, A pr. 2008
TC1163/TC1164
32-Bit Single-Chip Microcontroller
TriCore
Microcontrollers
TC1163/TC1164
Preliminary
TC1163/TC1164 Data Sheet
Revision History: V1.0, 2008-04
Previous Version: V0.3 2007-03
Page
7
8, 10
Subjects (major changes since last revision)
VSSOSC3 is deleted from the TC1163/TC1164 Logic Symbol.
TDATA0 of Pin 17, TCLK0 of Pin 20, TCLK0 of Pin 74 and TDATA0 of Pin
77 are updated in the Pinning Diagram and Pin Definition and Functions
Table.
Transmit DMA request in Block Diagram of ASC Interfaces is updated.
Alternate output functions in block diagram of SSC interfaces are updated.
Programmable baud rate of the MLI is updated.
TDATA0 and TCLK0 of the block diagram of MLI interfaces are updated.
The description for WDT double reset detection is updated.
The power sequencing details is updated.
MLI timing, maximum operating frequency limit is extended, t31 is added.
Thermal resistance junction leads is updated.
53
55
61
62
74
111
122
126
Trademarks
TriCore® is a trademark of Infineon Technologies AG.
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Data Sheet
V1.0, 2008-04
TC1163/TC1164
Preliminary
Table of Contents
Table of Contents
1
2
2.1
2.2
2.3
2.4
2.5
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.4.1
3.3.4.2
3.3.5
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.13.1
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23
3.24
Summary of Features
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General Device Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pad Driver and Input Classes Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Architecture and On-Chip Bus Systems . . . . . . . . . . . . . . . . . . . .
On-Chip Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architectural Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Read the Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents of the Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the FPI Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segments 0 to 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Segment 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Map of the Local Memory Bus (LMB) . . . . . . . . . . . . . . . . . . .
Memory Protection System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Control Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller and Memory Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) . . . . . . . . . .
High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) . . . . . . . . .
Micro Second Bus Interface (MSC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MultiCAN Controller (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Link Serial Bus Interface (MLI0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functionality of GPTA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog-to-Digital Converter (ADC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Analog-to-Digital Converter Unit (FADC) . . . . . . . . . . . . . . . . . . . . . .
System Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-Chip Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generation and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Identification Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
24
24
25
27
27
29
30
32
32
37
42
46
46
49
51
53
55
57
59
61
63
64
67
69
71
74
75
76
77
78
80
83
84
Data Sheet
V1.0, 2008-04
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