Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
OKI Semiconductor
MS82V48540
393,216-Word
×
32-Bit
×
4-Bank FIFO-SGRAM
FEDS82V48540-01
Issue Date:Nov. 8, 2002
GENERAL DESCRIPTION
The MS82V48540 is a 48-Mbit system clock synchronous dynamic random access memory. In addition to the
conventional random read/write access function, the MS82V48540 provides the automatic row address increment
function and automatic bank switching function. Therefore, if once the row and column addresses are set,
continuous serial accesses are possible while banks are automatically switched till input of the Precharge
command. The MS82V48540 is ideal for digital camera and TV buffer memory applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
393,216 words
×
32 bits
×
4 banks memory (1,536 rows
×
256 columns
×
32 bits
×
4 banks)
Single 3.3 V
±0.3
V power supply
LVTTL compatible inputs and outputs
Programmable burst length (1, 2, 4, 8 and full page)
Programmable
CAS
latency (2, 3)
Automatic row address increment function and automatic bank switching function
Power Down operation and Clock Suspend operation
3,072 refresh cycles/64 ms
Auto refresh and self refresh capability
Package:
86-pin 400 mil plastic TSOP (II) (TSOPII86-P-400-0.50-K) (Product : MS82V48540-xTA)
x indicates speed rank.
PRODUCT FAMILY
Family
MS82V48540-7
MS82V48540-8
Max. Operating Frequency
143 MHz
125 MHz
Access Time
5 ns
6 ns
Package
86-pin Plastic TSOP (II) (400 mil)
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FEDS82V48540-01
OKI Semiconductor
MS82V48540
PIN DESCRIPTION
CLK
CS
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 – RA10
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and
read/write during column address latch time.
BA0 = “L”, BA1 = “L”: Bank A
BA0 = “H”, BA1 = “L”: Bank B
BA0 = “L”, BA1 = “H”: Bank C
BA0 = “H”, BA1 = “H”: Bank D
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the
clock signal.
DQM0 controls DQ0 to DQ7, DQM1 controls DQ8 to DQ15, DQM2 controls DQ16 to DQ23, and
DQM3 controls DQ24 to DQ31.
Data inputs/outputs are multiplexed on the same pin.
CKE
Address
BA0, BA1
RAS
CAS
WE
DQM0 –
DQM3
DQ0 – DQ31
*Notes: 1. When
CS
is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE,
DQM0, DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by BA0 and BA1.
BA0
0
1
0
1
BA1
0
0
1
1
Active, read or write
Bank A
Bank B
Bank C
Bank D
3. The auto precharge function is enabled or disabled by the A10/AP input when the read or
write command is issued.
A10/AP
0
1
0
1
0
1
0
1
BA0
0
0
1
1
0
0
1
1
BA1
0
0
0
0
1
1
1
1
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the active status.
After the end of burst, bank B is precharged automatically.
After the end of burst, bank C holds the active status.
After the end of burst, bank C is precharged automatically.
After the end of burst, bank D holds the active status.
After the end of burst, bank D is precharged automatically.
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