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IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
FEATURES:
•
•
•
•
IDT54/74FCT543T/AT/CT/DT
•
•
•
•
•
Std., A, C, and D grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 64mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
DESCRIPTION:
The FCT543T is a non-inverting octal transceiver built using an advanced
dual metal CMOS technology. This device contains two sets of eight D-type
latches with separate input and output controls for each set. For data flow
from A to B, for example, the A-to-B Enable (CEAB) input must be low in order
to enter data from A
0
–A
7
or to take data from B
0
–B
7
, as indicated in the
Function Table. With
CEAB
low, a low signal on the A-to-B Latch Enable
(LEAB) input makes the A-to-B latches transparent; a subsequent low-to-
high transition of the
LEAB
signal puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With
CEAB
and
OEAB
both
low, the 3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but uses the
CEBA, LEBA
and
OEBA
inputs.
FUNCTIONAL BLOCK DIAGRAM
DETAIL A
D
LE
A
0
Q
D
LE
Q
B
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
DETAIL A x 7
B
1
B
2
B
3
B
4
B
5
B
6
B
7
OEBA
OEAB
CEBA
LEBA
CEAB
LEAB
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-5489/2
© 2002 Integrated Device Technology, Inc.
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
OEBA
CEBA
27
NC
A
0
OEBA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
CEAB
GND
2
3
4
5
6
7
8
9
10
11
12
23
22
21
20
19
18
17
16
15
14
13
CEBA
B
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
LEAB
OEAB
A
1
A
2
A
3
NC
A
4
A
5
A
6
5
6
7
8
9
4
3
2
28
1
26
25
24
23
22
21
20
19
18
B
0
INDEX
Vcc
LEBA
1
24
V
CC
LEBA
B
1
B
2
B
3
NC
B
4
B
5
B
6
10
11
12
13
14
15
16
17
CEAB
OEAB
LEAB
GND
NC
A
7
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
PIN DESCRIPTION
Pin Names
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A
0
–A
7
B
0
–B
7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
2
B
7
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE
(1, 2)
Inputs
LEAB
X
H
X
L
H
For A-to-B (Symmetric with B-to-A)
CEAB
H
X
X
L
L
OEAB
X
X
H
L
L
Latch
Status
A-to-B
Storing
Storing
X
Transparent
Storing
Output
Buffers
B
0
–B
7
High Z
X
High Z
Current A Inputs
Previous* A Inputs
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA
and
OEBA.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(3-State output pins)
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min, I
IN
= -18mA
—
V
CC
= Max., V
IN
= GND or V
CC
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
Test Conditions
(1)
V
CC
= Min
I
OH
= –6mA MIL
V
IN
= V
IH
or V
IL
I
OH
= –8mA IND
I
OH
= –12mA MIL
I
OH
= –15mA IND
V
CC
= Min
I
OL
= 48mA MIL
V
IN
= V
IH
or V
IL
I
OL
= 64mA IND
(3)
V
CC
= Max., V
O
= GND
V
CC
= 0V, V
IN
or V
O
≤
4.5V
Min.
2.4
2
—
–60
—
Typ.
(2)
3.3
3
0.3
–120
—
Max.
—
—
0.55
–225
±1
V
mA
µA
Unit
V
V
OL
I
OS
I
OFF
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
3
IDT54/74FCT543T/AT/CT/DT
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max., Outputs Open
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (LEAB )
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
One Bit Toggling
at fi = 5MHz
50% duty cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (LEAB )
50% Duty Cycle
CEAB
and
OEAB
= GND
CEBA
= V
CC
Eight Bits Toggling
at fi = 2.5MHz
50% duty cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
1.5
3.5
mA
—
2
5.5
—
3.8
7.3
(5)
mA
—
6
16.3
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
∆I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
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