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H5PS1G63EFR-Y5Q

Description
DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84
Categorystorage    storage   
File Size844KB,63 Pages
ManufacturerSK Hynix
Websitehttp://www.hynix.com/eng/
Environmental Compliance
Download Datasheet Parametric View All

H5PS1G63EFR-Y5Q Overview

DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84

H5PS1G63EFR-Y5Q Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
Parts packaging codeBGA
package instructionTFBGA, BGA84,9X15,32
Contacts84
Reach Compliance Codeunknown
ECCN codeEAR99
access modeMULTI BANK PAGE BURST
Maximum access time0.45 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)333 MHz
I/O typeCOMMON
interleaved burst length4,8
JESD-30 codeR-PBGA-B84
length13 mm
memory density1073741824 bit
Memory IC TypeDDR DRAM
memory width16
Number of functions1
Number of ports1
Number of terminals84
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature95 °C
Minimum operating temperature-40 °C
organize64MX16
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTFBGA
Encapsulate equivalent codeBGA84,9X15,32
Package shapeRECTANGULAR
Package formGRID ARRAY, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply1.8 V
Certification statusNot Qualified
refresh cycle8192
Maximum seat height1.2 mm
self refreshYES
Continuous burst length4,8
Maximum standby current0.006 A
Maximum slew rate0.22 mA
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formBALL
Terminal pitch0.8 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm
Base Number Matches1
H5PS1G63EFR Series
1Gb DDR2 SDRAM
H5PS1G63EFR-xxC
H5PS1G63EFR-xxI
H5PS1G63EFR-xxL
H5PS1G63EFR-xxJ
[New Product]
H5PS1G63EFR-xxP
H5PS1G63EFR-xxQ
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.1 / July 2009
1
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