EEWORLDEEWORLDEEWORLD

Part Number

Search

PP2JM32FREQ2

Description
Parallel - Fundamental Quartz Crystal, 13MHz Min, 13.999MHz Max, ROHS COMPLIANT, MINIATURE PACKAGE-4
CategoryPassive components    Crystal/resonator   
File Size401KB,2 Pages
ManufacturerMtronPTI
Websitehttp://www.mtronpti.com
Environmental Compliance  
Download Datasheet Parametric View All

PP2JM32FREQ2 Overview

Parallel - Fundamental Quartz Crystal, 13MHz Min, 13.999MHz Max, ROHS COMPLIANT, MINIATURE PACKAGE-4

PP2JM32FREQ2 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
package instructionROHS COMPLIANT PACKAGE-4
Reach Compliance Codeunknown
Other featuresAT-CUT CRYSTAL
Ageing2 PPM/YEAR
Crystal/Resonator TypePARALLEL - FUNDAMENTAL
Drive level100 µW
frequency stability0.005%
frequency tolerance30 ppm
JESD-609 codee4
load capacitance32 pF
Manufacturer's serial numberPP
Installation featuresSURFACE MOUNT
Maximum operating frequency13.999 MHz
Minimum operating frequency13 MHz
Maximum operating temperature60 °C
Minimum operating temperature-10 °C
physical sizeL6.0XB3.5XH1.2 (mm)/L0.236XB0.138XH0.047 (inch)
Series resistance50 Ω
surface mountYES
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
PP & PR Surface Mount Crystals
3.5 x 6.0 x 1.2 mm
Miniature low profile package (2 & 4 Pad)
RoHS Compliant
Wide frequency range
PCMCIA - high density PCB assemblies
PR (2 Pad)
PP (4 Pad)
Available Stabilities vs. Temperature
A = Available
N = Not Available
MtronPTI reserves the right to make changes to the product(s) and service(s) described herein without notice. No liability is assumed as a result of their use or application.
Please see
www.mtronpti.com
for our complete offering and detailed datasheets. Contact us for your application specific requirements: MtronPTI
1-800-762-8800.
Revision: 7-29-08
【Design Tools】 Comprehensive FPGA learning materials
FPGA implementation of 800Mbps quasi-cyclic LDPC code encoderFPGA design and implementation of CCSDS satellite-borne image compression moduleResearch on speech recognition system based on FPGA and Nio...
GONGHCU FPGA/CPLD
Share the process of WEBENCH design + hotswap design 1
[i=s] This post was last edited by accboy on 2014-8-21 11:35 [/i] [size=14px]This design, which means hot-swap controller, is used to limit inrush current by controlling an external FET. [/size][size=...
accboy Analogue and Mixed Signal
Linux kernel programming
rt, a book on Linux kernel programming...
wjwbin Linux and Android
500rmb please help me make a program!!!
I am a mechanical engineering student and I chose a terrible topic for my graduation project, lane departure warning system based on DSP. I have a tms3200m642 board, an xDS510 emulator, a camera, a mo...
chguanhao DSP and ARM Processors
I want to write a host computer for 430 serial communication... Could you please tell me which language to use?
[i=s]This post was last edited by huixianfxt on 2014-1-13 10:07[/i] The function is that the PC receives the data transmitted by the serial port, and displays the data on the PC (that is, a changing c...
huixianfxt Microcontroller MCU
The 4th Graphical System Design Tour Seminar
Event time/location: 2010/04/06 14:00 Conference Center on the 2nd floor of Wuxi Courtyard Marriott Hotel (No. 335, Zhongshan Road, Wuxi) 2010/04/07 14:00 Friendship Hall on the 4th floor of Nanjing Z...
yoselin Robotics Development

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 258  1624  2155  2717  2822  6  33  44  55  57 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号