21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74LVC00A
Fast CMOS 3.3V Quad
2-Input Positive NAND Gates
Product Features
• Functionally compatible with LCX family of products
• 1.65V - 3.6V V
CC
supply operation, –40°C to 85°C
• ESD Protection exceeds 2000V, Human Body Model
200V, Machine Model
• Inputs accept up to 5.5V
• Balanced sink and source output drives (24mA)
• Low ground bounce outputs, <0.8V @ 3.3V, 25°C
• Supports live insertion
• Packages available:
– 14-pin 173-mil wide plastic TSSOP (L)
– 14-pin 150-mil wide plastic SOIC (W)
Product Description
Pericom Semiconductor’s PI74LVC series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving high speed while maintaining low power
operation.
The PI74LVC00A is a quad 2-input positive NAND gate that
performs the Boolean function Y = A · B or Y = A + B in positive logic.
Inputs can be driven from either 3.3V or 5.0V devices allowing the
PI74LVC00A to be used as a translator in a mixed 3.3V/5.0V system.
Logic Diagram
Each Gate (Positive Logic)
A
Y
B
Pin Configuration
1A
1B
1Y
2A
1
2
3
4
5
6
7
14-Pin
L, W
14
13
12
11
10
9
8
VCC
4B
4A
4Y
3B
3A
3Y
Truth Table
(Each Gate)
Inputs
A
H
L
X
Notes:
H = HIGH Logic Level
L = LOW Logic Level
X = Don't Care
2B
2Y
B
H
X
L
Output
Y
L
H
H
GND
1
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PI74LVC00A
Fast CMOS 3.3V Quad
2-Input Positive NAND Gates
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, V
CC
............................................................ –0.5V to 6.5V
Input voltage range, V
I(1)
.............................................................. –0.5V to 6.5V
Output voltage range, V
O(1,2)
............................................. –0.5V to V
CC
+0.5V
Input clamp current, I
IK
(V
I
<0) ............................................................... –50mA
Output clamp current, I
OK
(V
O
<0) .......................................................... –50mA
Continuous output current, I
O
................................................................ ±50mA
Continuous current through V
CC
or GND .............................................. ±100mA
Package thermal impedance,
θ
JA(3)
: W package ................................. 113°C/W
L package .................................... 100°C/W
Storage Temperature range, T
stg ................................................................
65°C to 150°C
Notes:
Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1. The Input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V
CC
is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
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PI74LVC00A
Fast CMOS 3.3V Quad
2-Input Positive NAND Gates
Recommended Operating Conditions
(4)
Parame te r
V
CC
De s cription
Supply Voltage
Operating
Data retention only
V
CC
= 1.65V to 1.95V
V
IH
High- level Input Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 1.65V to 1.95V
V
IL
Low- level Input Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
I
V
O
Input Voltage
Output Voltage
V
CC
= 1.65V
I
OH
High- level output current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 1.65V
I
OL
Low- level output current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
∆
t /
∆
v
M in.
1.65
1. 5
0.65 x V
CC
1.7
2.0
M a x.
3.6
Units
0.35 x V
CC
0.7
0.8
0
0
5.5
V
CC
–4
–8
– 12
– 24
4
8
12
24
0
–40
10
85
V
mA
Input transition rise or fall time
Operating free- air temperature
ns/V
°C
T
A
Note:
4. All unused inputs must be held at V
CC
or GND to ensure proper device operation.
3
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PI74LVC00A
Fast CMOS 3.3V Quad
2-Input Positive NAND Gates
DC Electrical Characteristics
(Over Recommended Operating Free-Air Temperature Range, unless otherwise noted)
Parame te rs
Te s t Conditions
I
OH
= –100
µA
I
OH
= –4mA
V
OH
I
OH
= –8mA
I
OH
= –12mA
I
OH
= –24mA
I
OL
= 100µA
I
OL
= 4mA
V
OL
I
OL
= 8mA
I
OL
= 12mA
I
OL
= 24mA
I
I
I
CC
∆I
CC
C
I
V
I
= 5.5
V
or GND
V
I
= V
CC
or GND
I
O
= 0
V
CC
1.65V to 3.6V
1.65V
2.3V
2.7V
3V
3V
1.65V to 3.6V
1.65V
2.3V
2.7V
3V
3.6V
3.6V
2.7V to 3.6V
3.3V
3
M in.
V
CC
–0.2V
1.2
1.7
2.2
2.4
2.2
0.2
0.45
0.7
0.4
0.55
±5
10
500
pF
µA
V
Typ.†
M a x.
Units
One input a V
CC
–0.6V
Other inputs at V
CC
or GND
V
I
= V
CC
or GND
†
All typical values are measured at V
CC
= 3.3V, T
A
= 25°C
Switching Characteristics
(Over recommended operating free-air temperature range,unless otherwise noted, see Figures 1 through 3)
Parame te rs
t
pd
tsk(o)
§
From
(Input)
A or B
V
CC
= 1.8V ±0.15V V
CC
= 2.5V ±0.2V
To
(Output)
M in.
M a x.
M in.
M a x.
Y
1
12.5
1
6.4
V
CC
= 2.7V
M in.
1
M a x.
5.1
V
CC
= 3.3V ±0.3V
M in.
1
M a x.
4.3
1
Units
ns
§
Skew between any two outputs of the same package switching in the same direction.
Operating Characteristics, T
A
= 25°C
Parame te r
C
pd
De s cription
Power Dissipation Capacitance per gate
Te s t
Conditions
f = 10 MHz
V
CC
= 1.8V
Typ.
28
V
CC
= 2.5V
Typ.
34
V
CC
= 3.3V
Typ.
42
pF
Units
4
PS8602
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PI74LVC00A
Fast CMOS 3.3V Quad
2-Input Positive NAND Gates
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8V ±0.15V
2xVCC
Open
GND
1kΩ
From Output
Under Test
C
L
= 30pF
(See Note A)
S1
Te s t
1kΩ
S1
Open
2 x V
CC
GND
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
Load Circuit
Timing
Input
t
su
Data
Input
V
CC
V
CC
/2
0V
t
h
V
CC
V
CC
/2
V
CC
/2
0V
t
W
V
CC
Input
V
CC
/2
V
CC
/2
0V
Voltage Waveforms
Pulse Duration
Voltage Waveforms
Setup and Hold Times
V
CC
Input
V
CC
/2
t
PLH
V
CC
/2
t
PHL
Output
V
CC
/2
V
CC
/2
V
OL
t
PLH
V
CC
/2
0V
t
PHL
V
OH
Output
V
CC
/2
V
OL
V
OH
Output
Waveform 1
S1 at 2 x V
CC
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
Output
Control
(Low Level
Enabling)
V
CC
V
CC
/2
t
PZL
V
CC
/2
t
PZH
V
CC
/2
V
CC
/2
0V
t
PLZ
V
CC
V
OL
+0.15V
t
PHZ
V
OH
–0.15V
V
OH
0V
V
OL
Voltage Waveforms
Propagation Delay Times
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50Ω, t
R
≤
2.0ns, t
F
≤
2.0ns.
D. Outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
F. t
PZL
and t
PZH
are the same as t
en
G. t
PLH
and t
PHL
are the same as t
pd
H. Not all parameters and waveforms are applicable to all devices.
5
PS8602
03/17/03
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