71V546S117PFGI datasheet, PDF - EEWORLD Datasheet

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71V546S117PFGI: DescriptionZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100; Categorystorage storage; File Size184KB，21 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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71V546S117PFGI Overview

ZBT SRAM, 128KX36, 4.5ns, CMOS, PQFP100, 14 X 20 MM, ROHS COMPLIANT, PLASTIC, TQFP-100

71V546S117PFGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	QFP
package instruction	LQFP, QFP100,.63X.87
Contacts	100
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	4.5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	117 MHz
I/O type	COMMON
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	4718592 bit
Memory IC Type	ZBT SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP100,.63X.87
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.045 A
Minimum standby current	3.14 V
Maximum slew rate	0.285 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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128K x 36, 3.3V Synchronous

IDT71V546S/XS

SRAM with ZBT™ Feature,

™

Burst Counter and Pipelined Outputs

Features

128K x 36 memory configuration, pipelined outputs

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read

cycles

Internally synchronized registered outputs eliminate the

need to control

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW

) control (May tie active)

Three chip enables for simple depth expansion

Single 3.3V power supply (±5%)

Packaged in a JEDEC standard 100-pin TQFP package

clock cycle, and two cycles later its associated data cycle occurs, be it

read or write.

The IDT71V546 contains data I/O, address and control signal regis-

ters. Output enable is the only asynchronous signal and can be used to

disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V546 to be

suspended as long as necessary. All synchronous inputs are ignored

when

CEN

is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE

, CE

) that allow the user

to deselect the device when desired. If any one of these three is not active

when ADV/LD is low, no new memory operation can be initiated and any

burst that was in progress is stopped. However, any pending data

transfers (reads or writes) will be completed. The data bus will tri-state two

cycles after the chip is deselected or a write initiated.

The IDT71V546 has an on-chip burst counter. In the burst mode, the

IDT71V546 can provide four cycles of data for a single address presented

to the SRAM. The order of the burst sequence is defined by the

LBO

input

pin. The

LBO

pin selects between linear and interleaved burst sequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW) or increment the internal burst counter (ADV/LD = HIGH).

The IDT71V546 SRAM utilizes IDT's high-performance, high-volume

3.3V CMOS process, and is packaged in a JEDEC standard 14mm x

20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.

◆

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to

eliminate dead bus cycles when turning the bus around between reads

and writes, or writes and reads. Thus it has been given the name ZBT

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

Pin Description Summary

- A

, CE

R/W

CEN

CLK

ADV/LD

LBO

I/O

- I/O

, I/O

- I/O

Address Inputs

Three Chip Enables

Output Enable

Read/Write Signal

Clock Enable

Individual Byte Write Selects

Clock

Advance Burst Address / Load New Address

Linear / Interleaved Burst Order

Data Input/Output

3.3V Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Synchronous

Static

3821 tbl 01

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

OCTOBER 2008

DSC-3821/05

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