70V06S25PF9 datasheet, PDF - EEWORLD Datasheet

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70V06S25PF9: DescriptionDual-Port SRAM, 16KX8, 25ns, CMOS, PQFP64, TQFP-64; Categorystorage storage; File Size166KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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70V06S25PF9 Overview

Dual-Port SRAM, 16KX8, 25ns, CMOS, PQFP64, TQFP-64

70V06S25PF9 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	TQFP-64
Contacts	64
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	25 ns
Other features	INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	14 mm
memory density	131072 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	64
word count	16384 words
character code	16000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16KX8
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	240
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	14 mm
Base Number Matches	1

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HIGH-SPEED 3.3V

16K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT70V06S/L

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15/20/25/35/55ns (max.)

– Industrial: 20/25ns (max.)

Low-power operation

– IDT70V06S

Active: 400mW (typ.)

Standby: 3.3mW (typ.)

– IDT70V06L

Active: 380mW (typ.)

Standby: 660µW (typ.)

IDT70V06 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆

M/S = V

for

BUSY

output flag on Master

M/S = V

for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Battery backup operation—2V data retention

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

13L

(1,2)

I/O

Control

I/O

-I/O

BUSY

13R

(1,2)

Address

Decoder

MEMORY

ARRAY

Address

Decoder

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

outputs and

INT

outputs are non-tri-stated push-pull.

M/S

SEM

INT

(2)

2942 drw 01

OCTOBER 2008

DSC-2942/9

6.07

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