IDT54FCT163344AEB datasheet, PDF

EEWORLDEEWORLD

Datasheet

Datasheet> All Categories > logic> logic> IDT54FCT163344AEB

Preview

IDT54FCT163344AEB: DescriptionLow Skew Clock Driver, FCT Series, 8 True Output(s), 0 Inverted Output(s), CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56; Categorylogic logic; File Size197KB，8 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric Compare View All

IDT54FCT163344AEB Overview

Low Skew Clock Driver, FCT Series, 8 True Output(s), 0 Inverted Output(s), CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56

IDT54FCT163344AEB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DFP
package instruction	0.025 INCH PITCH, CERPACK-56
Contacts	56
Reach Compliance Code	not_compliant
series	FCT
Input adjustment	STANDARD
JESD-30 code	R-GDFP-F56
JESD-609 code	e0
length	18.415 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Number of functions	4
Number of inverted outputs
Number of terminals	56
Actual output times	8
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output characteristics	3-STATE
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DFP
Encapsulate equivalent code	FL56,.4,25
Package shape	RECTANGULAR
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/3.3 V
propagation delay (tpd)	5.1 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.5 ns
Filter level	38535Q/M;38534H;883B
Maximum seat height	2.413 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	FLAT
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	9.652 mm
Base Number Matches	1

Preview

Download Datasheet

View All

IDT54FCT163344AEB Related Products

	IDT54FCT163344AEB	IDT54FCT163344CEB	IDT54FCT163344EB
Description	Low Skew Clock Driver, FCT Series, 8 True Output(s), 0 Inverted Output(s), CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56	Low Skew Clock Driver, FCT Series, 8 True Output(s), 0 Inverted Output(s), CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56	Low Skew Clock Driver, FCT Series, 8 True Output(s), 0 Inverted Output(s), CMOS, CDFP56, 0.025 INCH PITCH, CERPACK-56
Is it Rohs certified?	incompatible	incompatible	incompatible
Parts packaging code	DFP	DFP	DFP
package instruction	0.025 INCH PITCH, CERPACK-56	0.025 INCH PITCH, CERPACK-56	0.025 INCH PITCH, CERPACK-56
Contacts	56	56	56
Reach Compliance Code	not_compliant	not_compliant	not_compliant
series	FCT	FCT	FCT
Input adjustment	STANDARD	STANDARD	STANDARD
JESD-30 code	R-GDFP-F56	R-GDFP-F56	R-GDFP-F56
JESD-609 code	e0	e0	e0
length	18.415 mm	18.415 mm	18.415 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Number of functions	4	4	4
Number of terminals	56	56	56
Actual output times	8	8	8
Maximum operating temperature	125 °C	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C	-55 °C
Output characteristics	3-STATE	3-STATE	3-STATE
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED
encapsulated code	DFP	DFP	DFP
Encapsulate equivalent code	FL56,.4,25	FL56,.4,25	FL56,.4,25
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	FLATPACK	FLATPACK	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	3/3.3 V	3/3.3 V	3/3.3 V
propagation delay (tpd)	5.1 ns	4.6 ns	7 ns
Certification status	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.5 ns	0.35 ns	0.75 ns
Filter level	38535Q/M;38534H;883B	38535Q/M;38534H;883B	38535Q/M;38534H;883B
Maximum seat height	2.413 mm	2.413 mm	2.413 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	MILITARY	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	FLAT	FLAT	FLAT
Terminal pitch	0.635 mm	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	9.652 mm	9.652 mm	9.652 mm
Base Number Matches	1	1	1

Recommended Resources

Apply LOGO! Automatic gating circuit a

μPC1490HA (TV) infrared remote control receiving signal processing circuit

Door and window anti-theft alarm circuit

RTD and AD208 isolation amplifier circuit

CW200 integrated regulated power supply using PNP power transistor for current expansion

Computer motherboard circuit diagram 440GX_17

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components