M36L0R7060U1 M36L0R7060L1
M36L0R7050U1 M36L0R7050L1
128 Mbit (Mux I/O, Multiple Bank, Multi-Level, Burst) Flash
memory, 32 or 64 Mbit PSRAM, 1.8V supply Multi-Chip Package
Preliminary Data
Feature summary
■
Multi-Chip Package
– 1 die of 128 Mbit (8Mb x16, Mux I/O
Multiple Bank, Multi-level, Burst) Flash
Memory
– 1 die of 32 or 64Mbit Mux I/O, Burst
Pseudo SRAM
Supply voltage
– V
DDF
= V
DDP
= V
DDQF
= 1.7 to 1.95V
– V
PPF
= 9V for fast program
Electronic signature
– Manufacturer Code: 20h
– Device Codes (Top Flash Configuration):
M36L0R7060U1: 882Eh,
M36L0R7050U1: 882Eh
– Device Codes (Bottom Flash Configuration)
M36L0R7060L1: 882Fh
M36L0R7050L1: 882Fh
ECOPACK® package
■
FBGA
TFBGA88 (ZAM)
8 x 10mm
■
■
■
Dual operations
– program/erase in one Bank while read in
others
– No delay between Read and Write
operations
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP
F
for Block Lock-Down
– Absolute Write Protection with V
PPF
= V
SS
Common Flash Interface (CFI)
■
■
Flash memory
■
■
Multiplexed address/data
Synchronous / asynchronous read
– Synchronous Burst Read mode: 66MHz
– Random Access: 85ns
Synchronous burst read suspend
programming time
– 10µs typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
100,000 program/erase cycles per block
■
■
■
■
PSRAM
Access time: 70ns
Synchronous modes:
– Synchronous Write: continuous burst
– Synchronous Read: continuous burst or
fixed length: 4, 8 or 16 Words for 32 Mbit
devices or 4, 8,16 or 32 Words for 64 Mbit
devices
– Maximum Clock Frequency: 83MHz
Low power consumption
Low power features
– Partial Array Self-Refresh (PASR)
– Deep Power-Down (DPD) Mode
– Automatic Temperature-compensated Self-
Refresh
■
■
■
■
June 2006
Rev 1
1/22
www.st.com
1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
Contents
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
Address Inputs (ADQ0-ADQ15 and A16-A22) . . . . . . . . . . . . . . . . . . . . . 10
Data Input/Output (ADQ0-ADQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash memory Chip Enable (E
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Output Enable (G
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Enable (W
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Write Protect (WP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory Reset (RP
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Chip Enable (E
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PSRAM Output Enable (G
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSRAM Write Enable (W
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSRAM Upper Byte Enable (UB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSRAM Lower Byte Enable (LB
P
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PSRAM Configuration Register Enable (CR
P
) . . . . . . . . . . . . . . . . . . . . . 12
V
DDF
Flash memory Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
CCP
PSRAM Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
V
DDQF
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
PPF
Flash memory Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . 13
V
SS
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
SSQ
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
4
5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
Contents
6
7
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
List of tables
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating modes - Standard Asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Stacked TFBGA88 8 × 10mm - 8 × 10 active ball array, 0.8mm pitch, package data . . . . 19
Part numbering scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4/22
M36L0R7060U1, M36L0R7060L1, M36L0R7050U1, M36L0R7050L1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
TFBGA88 8 × 10mm, 8 × 10 ball array - 0.8mm pitch, bottom view package outline. . . . . 19
5/22
MicroPython Open Source section
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