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UL62H1616AJK35

Description
Standard SRAM, 64KX16, 35ns, CMOS, PDSO44, 0.400 INCH, SOJ-44
Categorystorage    storage   
File Size195KB,10 Pages
ManufacturerAlliance Memory
Download Datasheet Parametric View All

UL62H1616AJK35 Overview

Standard SRAM, 64KX16, 35ns, CMOS, PDSO44, 0.400 INCH, SOJ-44

UL62H1616AJK35 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeSOJ
package instructionSOJ,
Contacts44
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time35 ns
JESD-30 codeR-PDSO-J44
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width16
Number of functions1
Number of terminals44
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize64KX16
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal locationDUAL
Maximum time at peak reflow temperature30
Base Number Matches1
Preliminary
Features
!
65536 x 16 bit static CMOS RAM
!
15, 20 and 35 ns Access Time
!
Common data inputs and
!
!
!
!
!
UL62H1616A
Low Voltage Automotive Fast 64K x 16 SRAM
Description
The UL62H1616A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Lower / Upper Byte Read
- Word Read
- Lower / Upper Byte Write
- Word Write
- Standby
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. During the active state
E = L and W = H each address
change leads to a new Read cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G. If LB = L the data lower byte will
be available at the outputs DQ0-
DQ7, on UB = L the data upper
byte appear at the outputs DQ8-
DQ15. After the address change,
the data outputs go High-Z until the
new information is available. The
data outputs have no preferred
state. The Read cycle is finished by
the falling edge of W, or by the
rising edge of E, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
!
!
!
!
data outputs
Three-state outputs
Standby current < 150 µA
at 125°C
TTL/CMOS-compatible
Power supply voltage 3.3 V
Operating temperature range
K-Type:-40 °C to 85 °C
A-Type:-40 °C to 125 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package: TSOP II 44 (400 mil)
Pin Configuration
A4
A3
A2
A1
A0
E
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
W
A15
A14
A13
A12
n.c.
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
36
9
35
10
34
11
SOJ
33
12
TSOPII
32
13
31
14
15
30
29
16
28
17
18
27
19
26
20
25
21
24
22
23
A5
A6
A7
G
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
n.c.
A8
A9
A10
A11
n.c.
Pin Description
BGA
LB
DQ8
DQ9
VSS
VCC
G
UB
DQ10
DQ11
DQ12
A0
A3
A5
n.c.
n.c.
A14
A12
A9
A1
A4
A6
A7
n.c.
A15
A13
A10
A2
E
DQ1
DQ3
DQ4
DQ5
W
A11
n.c.
DQ0
DQ2
VCC
VSS
DQ6
DQ7
n.c.
Signal Name Signal Description
A0 - A15
DQ0 - DQ15
E
G
W
UB
LB
VCC
VSS
n.c.
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Upper Byte Enable
Lower Byte Enable
Power Supply Voltage
Ground
not connected
DQ14 DQ13
DQ15
n.c.
n.c.
A8
Top View
Top View
October 20, 2003
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