EDI7C32128C
128Kx32 Flash
Features
128Kx32 bit Flash
• Fast Access Times: 60, 70, 90, 120 and 150ns
• Individual Byte Selects (x8, x16, x32)
• 100,000 Erase/Program Cycles minimum
• Output Enable Function
• TTL Compatible Inputs and Outputs
• 5V Programming
Sector Architecture
• 8 Equal Size Sectors of 16K bytes
• Sectors can be Concurrently Erased in
any Combination
• Supports Full Chip Erase
High Density MCM-C Packaging <0.99 in.sq.
• 68 lead CQFP, No. 405
• Multiple Ground Pins for Maximum Noise Immunity
Single +5V (±10%) Supply Operation
DSCC Drawing 5962-94716
128Kx32 High Speed
Flash Module
The EDI7C32128C is a high speed, high performance,
four megabit density Flash module, organized as 512Kx32 bits,
containing four 128Kx8 die mounted in a package.
Four Chip Enables are provided to independently enable
each of the four bytes. Reading or writing can be executed on
an individual byte or any combination of bytes through proper
use of the chip and write enables.
Fully asynchronous circuitry is used, requiring no clocks or
refreshing for operation and providing equal access and cycle
times for ease of use.
The EDI7C32128C is offered in a 68 lead CQFP package
which enables 4 megabits of memory to be placed in less than
0.99 square inches of space, respectively.
The device may be screened in accordance with MIL-
PRF-38535. This device is based on the AMD AM29F010 part.
Pin Names
AØ-A16
EØ-E3
WØ-W3
G
DQØ-DQ31
VCC
VSS
NC
AØ-A18
A16
G
19
17
Pin Configuration and Block Diagram
E3\
WO
\
VCC
A3
A4
A5
E2\
VSS
A9
A10
NC
AO
A1
A2
A6
A7
A8
Address Inputs
Chip Enables
Write Enables
Output Enable
Common Data Input/Output
Power (+5V±10%)
Ground
No Connection
68
67
66
65
64
63
62
DQØ
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9
8
7
6
5
4
3
2
1
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
WØ
EØ
8
DQØ-DQ7
W1
E1
8
DQ8-DQ15
W2
E2
8
DQ16-DQ23
E1\
NC
A17*)
W1\
W2\
W3\
NC
A18*)
VSS
NC
NC
VCC
A11
A12
A13
A14
A15
A16
EO
\
G\
W3
E3
8
DQ24-DQ31
Electronic Designs, Incorporated
• One Research Drive • Westborough, MA 01581 USA • 508-366-5151 • FAX 508-836-4850 •
http://www.electronic-designs.com
1
EDI7C32128C Rev. 0 4/98 ECO#10103
Absolute Maximum Ratings*
Voltage on any pin relative to VSS
(1)
-2.0V to 7.0V
Operating Temperature TA (Ambient)
Commercial
0°C to + 70°C
Industrial
-40°C to +85°C
Military
-55°C to +125°C
Storage Temperature
-65°C to +150°C
Power Dissipation
1.1 Watts Max@5MHz
(2)
A9 Voltage for Sector Protect
-2.0V to +14.0V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. Minimum DC voltage on input or I/O pins is -0.5V during voltage transitions, inputs or
I/O pins may undershoot Vss to -2.0V for periods of up to 20ns. Maximum DC
voltage on output and I/O pins is Vcc+0.5V during voltage transitions, outputs may
overshoot to Vcc+2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may
overshoot Vss to -2V for periods up to 20ns. Maximum DC input voltage on A9 is
+13.5V which may overshoot to +14.0 for periods up to 20ns.
Recommended DC Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
A9 Voltage for
Sector Protect
Sym Min
VCC 4.5
VSS
0
VIH 2.0
VIL -0.5
+11.5
Typ Max Units
5.0 5.5
V
0
0
V
-- VCC+0.5
V
--
0.8
V
--
+12.5
V
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
1.
2.
3.
4.
5.
Vz is programmable from +2V to +7V.
I
OL
and I
OH
are programmable from 0 to 16mA.
Tester impedance is Zo=75ohms.
Vz is typically the midpoint of V
OL
and V
OH
.
I
OL
and I
OH
are adjusted to simulate a
Figure 1
typical resistive load circuit.
6. ATE tester includes jig capacitance.
To Device Under
Test
VSS to 3.0V
5ns
1.5V
Figure 1
Current Source
I
OL
V
Z
~1.5V
~
DC Electrical Characteristics
Parameter
Operating Power
Supply Current – x32
Standby (TTL) Power
Supply Current
Full Standby Power
Supply Current
Input Leakage Current
Output Leakage Current
Output High Volltage
Output Low Voltage
Sym
ICC1
ICC2
ICC3
ILI
ILO
VOH
VOL
Conditions
G= VIL, f=5MHz
60-150ns
E = VIL
E=VIL, G=VIH
60-150ns
f=5MHz, VCC=5.5V
E=VIH
60-150ns
f=5MHz, VCC=5.5V
VIN = 0V to VCC
V I/O = 0V to VCC
IOH = -2.5mA, VCC=4.5V
IOL =12.0mA, VCC=4.5V
Min
C
EFF
50pF
I
OH
Current Source
Typ
Max
140
200
6.5
mA
±10
±10
0.45
Units
mA
mA
mA
µA
µA
V
V
--
--
0.85xVCC
--
--
Truth Table
G
X
H
L
H
E
H
L
L
L
W
Mode
X
Standby
H Output Deselect
H
Read
L
Write
Output
High Z
High Z
DOUT
DIN
Power
ICC2, ICC3
ICC1
ICC1
ICC1
Capacitance
(f=1.0MHz, VIN=VCC or VSS)
Parameter
Address Lines
Data Lines
Chip & Write Enable Lines
Output Enable Line
These parameters are sampled, not 100% tested.
Sym Max
CI
50
CD/Q 20
E, W 20
G
50
Unit
pF
pF
pF
pF
EDI7C32128C
128Kx32 Flash
2
EDI7C32128C Rev. 0 4/98 ECO#10103
EDI7C32128C
128Kx32 Flash
AC Characteristics Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in High Z
(1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output High Z
(1)
Note 1. Parameter guaranteed, but not tested.
Symbol
JEDEC Alt.
TAVAV TRC
TAVQV TAA
TELQV TACS
TEHQZ TDF
TAVQX TOH
TGLQV TOE
TGHQZ TDF
60
Min Max
60
60
60
20
0
30
20
70ns
MinMax
70
70
70
20
0
35
20
90ns
Min Max
90
90
90
20
0
35
20
120ns
Min Max
120
120
120
30
0
50
30
150ns
Min Max
150
150
150
35
0
55
35
Units
ns
ns
ns
ns
ns
ns
ns
AC Waveforms for Read Operations
A
t
AA
E
G
W
Q
t
ACS
Write/Erase/Program Operation, W Controlled
A
E
G
W
Q
Notes:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. Dout is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
t
ACS
3
EDI7C32128C Rev. 0 4/98 ECO#10103
AC Characteristics Write Cycle
Parameter
Write Cycle Time
Chip Enable Setup Time
Chip Enable Pulse Width
Address Setup Time
Write Enable Setup Time
Address Hold Time
Write Pulse Width
Data Setup Time
Data Hold Time
Write Enable Pulse Width High
Output Enable Setup Time
Output Enable Hold Time
Sector Erase Time
Programming Time
Read Recovery Time Before Rewrite TGHWL
Vcc Setup Time
TVCS
1
Duration of Byte Programming Operation TWHWH
Symbol
JEDEC
Alt.
TAVAV TWC
TELWH TCS
TELEH TCP
TAVWL TAS
TWLEL TWS
TWHAX TAH
TWLWH TWP
TDVWH TDS
TWHDX TDH
TWHWL TWPH
TOES
TOEH
2
TWHWH
60ns
Min Max
60
0
30
0
0
45
30
30
0
20
0
10
2.2 60
12.5
0
50
14
70ns
Min Max
70
0
45
0
0
45
45
45
0
20
0
10
2.2 60
12.5
0
50
14
90ns
Min Max
90
0
45
0
0
45
45
45
0
20
0
10
2.2 60
12.5
0
50
14
120ns
Min Max
120
0
50
0
0
50
50
50
0
20
0
10
2.2 60
12.5
0
50
14
150ns
Min Max Units
150
ns
0
ns
50
ns
0
ns
0
ns
50
ns
50
ns
50
ns
0
ns
20
ns
0
ns
10
ns
2.2 60
s
12.5
s
0
ns
50
µs
14
µs
AC Waveforms Chip/Selector Erase Operations
A
E
G
W
Q
EDI7C32128C
128Kx32 Flash
4
EDI7C32128C Rev. 0 4/98 ECO#10103
EDI7C32128C
128Kx32 Flash
AC Waveforms for Data Polling during Embedded Algorithm Operations
E
G
W
t
ACS
Q
Alternate E Controlled Programming Operation Timing
A
W
t
GHWL
G
E
t
WPH
Q
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7 is the output of the complement of the data written to the device (for each chip).
4. Dout is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
5
EDI7C32128C Rev. 0 4/98 ECO#10103
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