datasheet
EEWORLDEEWORLDEEWORLD
Datasheet
Part Number

Keyword

Search
Keyword

Part Number

Search
Datasheet> All Categories > storage> storage> M2S28D30ATP-75
PDF
Preview

M2S28D30ATP-75

Description
128M Double Data Rate Synchronous DRAM
Categorystorage    storage   
File Size1MB，36 Pages
ManufacturerMitsubishi
Websitehttp://www.mitsubishielectric.com/semiconductors/
Download Datasheet Parametric Compare View All

M2S28D30ATP-75 Overview

128M Double Data Rate Synchronous DRAM

M2S28D30ATP-75 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMitsubishi
Parts packaging codeTSOP2
package instructionSOP, TSSOP66,.46
Contacts66
Reach Compliance Codeunknow
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
interleaved burst length2,4,8
JESD-30 codeR-PDSO-G66
JESD-609 codee0
memory density134217728 bi
Memory IC TypeDDR DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals66
word count16777216 words
character code16000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16MX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeTSSOP66,.46
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5 V
Certification statusNot Qualified
refresh cycle4096
self refreshYES
Continuous burst length2,4,8
Maximum standby current0.02 A
Maximum slew rate0.17 mA
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED

M2S28D30ATP-75 Preview

DDR SDRAM (Rev.0.1)
Jun,'00
Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
M2S28D20ATP is a 4-bank x 8388608-word x 4-bit,
M2S28D30ATP is a 4-bank x 4194304-word x 8-bit,
M2S28D40ATP is a 4-bank x 2097152-word x 16-bit,
double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are
referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output
data and data strobe are referenced on both edges of CLK. The M2S28D20/30/40ATP achieves very
high speed data rate up to 133MHz, and are suitable for main memory in computer systems.
FEATURES
- Vdd=Vddq=2.5V+0.2V
- Double data rate architecture;
two data transfers per clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received with data
- Differential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions
with CLK transitions edges of DQS
- Commands entered on each positive CLK edge;
- data and data mask referenced to both edges of DQS
- 4 bank operation controlled by BA0, BA1 (Bank Address)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst type- sequential / interleave (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 refresh cycles /64ms (4 banks concurrent refresh)
- Auto refresh and Self refresh
- Row address A0-11 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)
- SSTL_2 Interface
- 400-mil, 66-pin Thin Small Outline Package (TSOP II)
- FET switch control(/QFC) for x4/ x8
- JEDEC standard
MITSUBISHI ELECTRIC
1
DDR SDRAM (Rev.0.1)
Jun,'00
Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PIN CONFIGURATION(TOP VIEW)
x4
x8
x16
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU,/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU,/QFC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CLK
CLK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
66pin TSOP(II)
400mil width
x
875mil length
0.65mm
Lead Pitch
ROW
A0-11
Column
A0-9,11(x4)
A0-9 (x8)
A0-8 (x16)
CLK,/CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-7
DQS
DM
/QFC
Vref
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
: Data Strobe
: Write Mask
: FET Switch Control for x4/x8
: Reference Voltage
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Address Input
: Bank Address Input
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
2
DDR SDRAM (Rev.0.1)
Jun,'00
Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BLOCK DIAGRAM
DLL
DQ0 - 15
/QFC for x4/x8 UDQS,LDQS
I/O Buffer
QFC&QS Buffer
Memory
Array
Bank #0
Memory
Array
Bank #1
Memory
Array
Bank #2
Memory
Array
Bank #3
Mode Register
Control Circuitry
Address Buffer
Clock Buffer
A0-11
BA0,1
CLK, /CLK CKE
Control Signal Buffer
/CS /RAS /CAS /WE
UDM,
LDM
Type Designation Code
This rule is applied to only Synchronous DRAM family.
M 2 S 28 D 3 0 A TP -75
Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0
75: 133MHz@CL=2.5,100MHz@CL=2.0
Package Type TP: TSOP(II)
Process Generation
Function Reserved for Future Use
Organization 2 n 2: x4, 3: x8, 4: x16
DDR Synchronous DRAM
Density 28: 128M bits
Interface V:LVTTL, S:SSTL_3, _2
Memory Style (DRAM)
Mitsubishi Main Designation
MITSUBISHI ELECTRIC
3
DDR SDRAM (Rev.0.1)
Jun,'00
Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CLK and /CLK are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CLK and negative edge of /CLK. Output (read) data is referenced to
the crossings of CLK and /CLK (both directions of crossing).
Clock Enable: CKE controls internal clock. When CKE is low, internal
clock for the following cycle is ceased. CKE is also used to select auto /
self refresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select: When /CS is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9,11(x4), A0-9(x8) and A0-8(x16). A10 is also used to
indicate precharge option. When A10 is high at a read / write
command, an auto precharge is performed. When A10 is high at a
precharge command, all banks are precharged.
Bank Address: BA0,1 specifies one of four banks to which a command is
applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS
correspond to the data on DQ8-DQ15
FET Control: Optional. Output during every Read and Write access. Can
be used to control isolation switches on modules. Open drain output.
Input Data Mask: DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input only, the DM loading matches the DQ
and DQS loading. For the x16, LDM corresponds to the data on DQ0-
DQ7; UDM corresponds to the data on DQ8-DQ15.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
SSTL_2 reference voltage.
CLK, /CLK
Input
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
DQ0-15(x16),
DQ0-7(x8),
DQ0-3(x4),
Input
Input / Output
DQS
Input / Output
/QFC
Output
DM
Input
Vdd, Vss
VddQ, VssQ
Vref
Power Supply
Power Supply
Input
MITSUBISHI ELECTRIC
4
DDR SDRAM (Rev.0.1)
Jun,'00
Preliminary
MITSUBISHI LSIs
M2S28D20/ 30/ 40ATP
128M Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
The M2S28D20/30/40ATP provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Refresh Option @refresh command
Precharge Option @precharge or read/write command
define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,
READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge,
WRITEA)
.
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA
).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are generated
internally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

M2S28D30ATP-75 Related Products

M2S28D30ATP-75 M2S28D20ATP M2S28D20ATP-75 M2S28D30ATP M2S28D40ATP M2V28D40ATP-75 M2V28D30ATP-75 M2V28D20ATP-75 M2S28D40ATP-75
Description 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM 128M Double Data Rate Synchronous DRAM

Recommended Resources

The working principle of the microwave oven operation display circuit

Song and dance hall automatic fill light circuit

Switching regulated power supply composed of μA741

Watson FS80-40 floor fan circuit diagram

Welding seam position online identification circuit

Universal power load circuit using light bulbs

Nuvoton 003 Series Platform MS51 Replacement N76E003 Guide V1.0
Based on the N76E003 market, Nuvoton Technology launched the 003 series platform, which is a direct replacement for the N76E003AT20/N76E003AQ20. For hardware and software migration, please refer to th...
beiC 51mcu
Practical Guide for Motor Application Development - Based on WildFire STM32 Full Series Development Board
Motor is an electrical device used to convert electrical energy into mechanical energy, commonly known as a motor. Its main function is to generate driving torque as a power source for electrical appl...
arui1999 Download Centre
6~20GHz broadband low noise medium power amplifier
This paper introduces the development of a 6~20GHz microwave broadband low-noise, medium-power amplifier. Using microwave broadband matching and CAD technology, an amplifier that meets the requirement...
JasonYoo Analog electronics
I want to make a video processing embedded system based on FPGA, and also be able to implement my own watermark algorithm. Please give me some ideas!! Thank you
I hope to make an embedded video processing system, of course the lower the cost the better, I have no experience in this area before. I hope experts can give me some advice, such as what chips or wre...
cd0054115 Embedded System
Video frame synchronization
I am currently working on a frame synchronization product. I have searched the relevant principles online, but there are still some things I don't understand: 1: Are the points where digital video is ...
zhuxinyu2008 FPGA/CPLD
tmp006 issue
When debugging the tmp006 infrared temperature measurement chip, I encountered a strange phenomenon. The chip's sensitivity to light is stronger than heat? There is no change when it is placed in fron...
mario813 Analogue and Mixed Signal
Shortcut:   00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components

  1. 212U1002S328FN2
  2. HC49J/554DF4.40MHZ
  3. SL1-007-U190/01-88
  4. HTSHCR-145-S-14-230-T
  5. MWDM6L-130GS-0E5-18F
  6. M55342K02B300KRBS
  7. CMC-200/393ZY1210TF
  8. GUS-SL0B-01-8061-D
  9. SB4040PT_T0_00001
  10. D2541WRA-9P-2
  11. HR913550A
  12. 4D03WGF360JT5E

Popular Articles

  1. Real-time clock demonstration: millisecond timing output; serial port output; use of interrupts
  2. Function of material level switch
  3. Design of intelligent wiper based on 51 single chip microcomputer
  4. vivo X70 series new product launch conference
  5. Infineon launches new generation MOTIX™ half-bridge driver IC
  6. Sony: Xperia 10 II/10 III will be upgraded to Android 12 system
  7. Siemens PLC working mode
  8. Learn these and you will be a Tektronix oscilloscope expert! (Part 2)
  9. Analysis of the Working Principle of Mixed Signal Oscilloscope
  10. Qi® charging gets much-needed safety boost

Technical ResourceMore

  1. Simple network analyzer made of AD5933 (improved version)
  2. Q∕GDW 11147-2017 Design specification for distributed generation access to distribution network
  3. Inductor boost circuit principle
  4. Personal 3D connector library: XH2.54-5
  5. How to program MC68HC705J1A online
  6. Practical Software Testing Methods and Applications (Integration Testing)
  7. This is the source code for the MSP430F449 microcontroller using the clock crystal to obtain the real-time clock and on-chip ad conversion control
  8. Self-made 3D component library: AXIAL_RESISTOR(0_25W)
  9. 51 single chip microcomputer controls the source program of 18b20 temperature sensor
  10. Automotive transmission electronic control technology - Automatic transmission electronic control system

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

About Us Customer Service Contact Information Datasheet Sitemap LatestNews
Index Files: 1033  2920  2280  2561  120  21  59  46  52  3 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号