M29F100T
M29F100B
1 Mbit (128Kb x8 or 64Kb x16, Boot Block)
Single Supply Flash Memory
5V
±
10% SUPPLY VOLTAGE for PROGRAM,
ERASE and READ OPERATIONS
FAST ACCESS TIME: 70ns
FAST PROGRAMMING TIME
– 10
µ
s by Byte / 16
µ
s by Word typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-Byte or Word-by-Word
– Status Register bits and Ready/Busy Output
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main blocks
BLOCK, MULTI-BLOCK and CHIP ERASE
MULTI-BLOCK PROTECTION/TEMPORARY
UNPROTECTION MODES
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
LOW POWER CONSUMPTION
– Stand-by and Automatic Stand-by
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code, M29F100T: 00D0h
– Device Code, M29F100B: 00D1h
DESCRIPTION
The M29F100 is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byteor Word-
by-Word basis using only a single 5V V
CC
supply.
For Program and Erase operations the necessary
high voltages are generated internally. The device
can also be programmed in standard program-
mers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
July 1998
44
1
TSOP48 (N)
12 x 20 mm
SO44 (M)
Figure 1. Logic Diagram
VCC
16
A0-A15
W
E
G
RP
M29F100T
M29F100B
15
DQ0-DQ14
DQ15A–1
BYTE
RB
VSS
AI01974
1/30
M29F100T, M29F100B
Figure 2A. TSOP Pin Connections
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
48
NC
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
Figure 2B. TSOP Reverse Pin Connections
NC
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
1
48
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
W
RP
NC
NC
RB
NC
NC
A7
A6
A5
A4
A3
A2
A1
12
13
M29F100T
M29F100B
(Normal)
37
36
12
13
M29F100T
M29F100B
(Reverse)
37
36
24
25
AI01975
24
25
AI01976
Warning:
NC = Not Connected.
Warning:
NC = Not Connected.
Figure 2C. SO Pin Connections
Table 1. Signal Names
A0-A15
Address Inputs
Data Input/Outputs, Command Inputs
Data Input/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset / Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organisation
Supply Voltage
Ground
NC
RB
NC
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
1
43
2
42
3
41
4
5
40
6
39
7
38
8
37
36
9
35
10
11 M29F100T 34
12 M29F100B 33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
AI01977
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
NC
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
CC
V
SS
Warning:
NC = Not Connected.
2/30
M29F100T, M29F100B
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
(A9, E, G, RP)
(2)
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltages
Supply Voltage
A9, E, G, RP Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–0.6 to 7
–0.6 to 7
–0.6 to 13.5
Unit
°
C
°
C
°
C
V
V
V
Notes:
1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other
relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
DESCRIPTION
(Cont’d)
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase, Erase
Suspend and Resume are written to the device in
cycles of commandsto a Command Interfaceusing
standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm) and
SO44 packages. Both normal and reverse pinouts
are available for the TSOP48 package.
Organisation
The M29F100 is organised as 128Kb x8 or 64Kb
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is
selected and the address lines are DQ15A–1 and
A0-A15. The Data Input/Output signal DQ15A–1
acts as address line A–1 which selects the lower or
upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTE is High the memory uses the address
inputs A0-A15 and the Data Input/Outputs DQ0-
DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
AReset/Block TemporaryUnprotection RP tri-level
input provides a hardware reset when pulled Low,
and when held High (at V
ID
) temporarily unprotects
blocks previously protected allowing them to be
programed and erased. Erase and Program opera-
tions are controlled by an internal Program/Erase
Controller (P/E.C.). Status Register data output on
DQ7 provides a Data Polling signal, and DQ6 and
DQ2 provide Toggle signals to indicate the state of
the P/E.C operations. A Ready/Busy RB output
indicates the completion of the internal algorithms.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29F100T and M29F100B devices have an array
of 5 blocks, one Boot Block of 16 KBytes or 8
KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and one Main Blocks of 64 KBytes or 32
KWords. The M29F100T has the Boot Block at the
top of the memory address space and the
M29F100B locates the Boot Block starting at the
bottom. The memory maps are showed in Figure
3. Each block can be erased separately, any com-
bination of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the
P/E.C. The block erase operation can be sus-
pended in order to read from or program to any
block not being ersased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriatebus cycles: Read (Array, Electronic
Signature, Block Protection Status), Write com-
mand, Output Disable, Standby, Reset, Block Pro-
t ec t io n , Unp ro t e ct io n, P ro t e cti on Verif y,
Unprotection Verify and Block Temporary Unpro-
tection. See Tables 4 and 5.
3/30
M29F100T, M29F100B
Figure 3. Memory Map and Block Address Table (x8)
M29F100T
1FFFFh
16K BOOT BLOCK
1C000h
1BFFFh
8K PARAMETER BLOCK
1A000h
19FFFh
8K PARAMETER BLOCK
18000h
17FFFh
32K MAIN BLOCK
10000h
0FFFFh
64K MAIN BLOCK
00000h
00000h
04000h
03FFFh
08000h
07FFFh
06000h
05FFFh
10000h
0FFFFh
1FFFFh
M29F100B
64K MAIN BLOCK
32K MAIN BLOCK
8K PARAMETER BLOCK
8K PARAMETER BLOCK
16K BOOT BLOCK
AI01978
Table 3A. M29F100T Block Address Table
Address Range (x8)
00000h-0FFFFh
10000h-17FFFh
18000h-19FFFh
1A000h-1BFFFh
1C000h-1FFFFh
Address Range (x16)
0000h-7FFFh
8000h-BFFFh
C000h-CFFFh
D000h-DFFFh
E000h-FFFFh
A15
0
1
1
1
1
A14
X
0
1
1
1
A13
X
X
0
0
1
A12
X
X
0
1
X
Table 3B. M29F100B Block Address Table
Address Range (x8)
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
Address Range (x16)
0000h-1FFFh
2000h-2FFFh
3000h-3FFFh
4000h-7FFFh
8000h-FFFFh
A15
0
0
0
0
1
A14
0
0
0
1
X
A13
0
1
1
X
X
A12
X
0
1
X
X
4/30
M29F100T, M29F100B
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second,fourth and fifth
cycles are used to input Coded cycles to the C.I.
This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the ElectronicSignature
or Block ProtectionStatus), Program, Block Erase,
Chip Erase, Erase Suspend and Erase Resume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase
operations.The Status Register Data Polling, Tog-
gle, Error bits and the RB output may be read at
any time, during programming or erase, to monitor
the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interfacewhich iscommon to all instruc-
tions (see Table 8). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data, Electronic Signature or
Block Protection Status for Read operations. In
order to give additional data protection,the instruc-
tions for Program and Block or Chip Erase require
further command inputs. For a Programinstruction,
the fourth command cycle inputs the address and
data to be programmed. For an Erase instruction
(Block or Chip), the fourth and fifth cycles input a
further Coded sequence before the Erase confirm
command on the sixth cycle. Erasure of a memory
block may be suspended,in orderto read data from
another block or to program data in another block,
and then resumed.
When power is first applied or if V
CC
falls below
V
LKO
, the command interface is reset to Read
Array.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A15).
The address inputs for
the memory array are latched during a write opera-
tion on the falling edge of Chip Enable E or Write
Enable W. In Word-wide organisation the address
lines are A0-A15, in Byte-wide organisation
DQ15A–1 acts as an additional LSB address line.
When A9 is raised to V
ID
, either a Read Electronic
Signature Manufacturer or Device Code, Block
Protection Status or a Write Block Protection or
Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7).
T h e s e I n-
puts/Outputsare used in the Byte-wide and Word-
wide organisations. The input is data to be
programmed in the memory array or a command
to be written to the C.I. Both are latched on the
rising edge of Chip Enable E or Write Enable W.
The output is data from the Memory Array, the
Electronic Signature Manufacturer or Device
codes, the Block Protection Status or the Status
register Data Polling bit DQ7, the Toggle Bits DQ6
and DQ2, the Error bit DQ5 or the Erase Timer bit
DQ3. Outputs are valid when Chip Enable E and
Output Enable G are active. The output is high
impedance when the chip is deselected or the
outputsare disabled and when RP is at a Low level.
Data Input/Outputs (DQ8-DQ14 and DQ15A–1).
These Inputs/Outputs are additionally used in the
Word-wide organisation.When BYTEis High DQ8-
DQ14 and DQ15A–1 act as the MSB of the Data
Input or Output, functioning as described for DQ0-
DQ7 above, and DQ8-DQ15 are ’don’t care’ for
command inputs or status outputs. When BYTE is
Low, DQ8-DQ14 are high impedance, DQ15A–1 is
the Address A–1 input.
Chip Enable (E).
The Chip Enable input activates
the memory control logic, input buffers, decoders
and sense amplifiers. E High deselectsthe memory
and reduces the power consumptionto the standby
level. E can also be used to control writing to the
command register and to the memory array, while
W remains at a low level. The Chip Enable must be
forced to V
ID
during the Block Unprotection opera-
tion.
Output Enable (G).
The Output Enable gates the
outputs through the data buffers during a read
operation. When G is High the outputs are High
impedance. G must be forced to V
ID
level during
Block Protection and Unprotection operations.
Write Enable (W).
This input controls writing to the
Command Registerand Addressand Datalatches.
Byte/Word Organization Select (BYTE).
The
BYTE input selects the output configuration for the
device: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTE is Low, the Byte-wide mode is
selected and the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
5/30
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