EMCL13D2J-90.000M TR
Series
RoHS Compliant (Pb-free) 3.3V 6 Pad 5mm x 7mm
Plastic SMD LVPECL MEMS Oscillator
Frequency Tolerance/Stability
±50ppm Maximum over 0°C to +70°C
Duty Cycle
50 ±5(%)
RoHS
Pb
Packaging Options
Tape & Reel
EMCL13 D 2 J -90.000M TR
Nominal Frequency
90.000MHz
Logic Control / Additional Output
Standby (ST) and Complementary Output
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
90.000MHz
±50ppm Maximum over 0°C to +70°C (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency
Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year
Aging at 25°C, Reflow, Shock, and Vibration)
±1ppm First Year Maximum
+3.3Vdc ±0.3Vdc
80mA Maximum (Excluding Load Termination Current)
2.35Vdc Typical, Vcc-1.025Vdc Minimum
1.6Vdc Typical, Vcc-1.62Vdc Maximum
150pSec Typical, 300pSec Maximum (Measured over 20% to 80% of waveform)
50 ±5(%) (Measured at 50% of waveform)
50 Ohms into Vcc-2.0Vdc
LVPECL
Standby (ST) and Complementary Output
Vih of 70% of Vcc Minimum or No Connect to Enable Output and Complementary Output, Vil of 30% of Vcc
Maximum to Disable Output and Complementary Output (High Impedance)
30µA Maximum (ST) Without Load
0.2pSec Typical
2.0pSec Typical
1.5pSec Typical, 3.0pSec Maximum
20pSec Typical, 25pSec Maximum
1.7pSec Typical
1.4pSec Typical
1.1pSec Typical
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Logic Control / Additional Output
Output Control Input Voltage
Standby Current
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
RMS Phase Jitter (Fj = 637kHz to
10MHz; Random)
RMS Phase Jitter (Fj = 1MHz to
20MHz; Random)
RMS Phase Jitter (Fj = 1.875MHz to
20MHz; Random)
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Flammability
Mechanical Shock
Moisture Resistance
Moisture Sensitivity Level
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Thermal Shock
Vibration
MIL-STD-883, Method 3015, Class 2, HBM 2000V
UL94-V0
MIL-STD-883, Method 2002, Condition G, 30,000G
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003 (Six I/O Pads on bottom of package only)
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 1011, Condition B
MIL-STD-883, Method 2007, Condition A, 20G
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 1 of 6
EMCL13D2J-90.000M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUTS
V
OH
80%
50%
20%
V
OL
Q
OUTPUT STANDBY
(HIGH IMPEDANCE
STATE)
Q
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for Tri-State and Complementary Output
50 Ohms
Pin Connections
1 Tri-State
2 No Connect
3 Ground
4 Output
5 Complementary Output
6 Supply Voltage (V
DD
)
Oscilloscope
Frequency
Counter
Power
Supply
Supply
Voltage
(V
DD
)
Current
Meter
0.01µF
(Note 1)
0.1µF
(Note 1)
Complementary
Output
Probe 2
(Note 2)
Output
Probe 1
(Note 2)
50 Ohms
Switch
Power
Supply
Voltage
Meter
Power
Supply
Ground
Tri-State
No
Connect
Power
Supply
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass capacitor close (less than 2mm)
to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (>500MHz) passive probe is
recommended.
Note 3: Test circuit PCB traces need to be designed for a characteristic line impedance of 50 ohms.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 3 of 6
FPGA/CPLD
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