L-USS820FD-DB datasheet, PDF - EEWORLD Datasheet

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L-USS820FD-DB: DescriptionUSB Bus Controller, CMOS, PBGA48, LEAD FREE, TFSBGAC-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size828KB，56 Pages; ManufacturerLSC/CSI; Websitehttps://lsicsi.com; Environmental Compliance

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L-USS820FD-DB Overview

USB Bus Controller, CMOS, PBGA48, LEAD FREE, TFSBGAC-48

L-USS820FD-DB Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	LFBGA, BGA48,8X8,20
Contacts	48
Reach Compliance Code	unknown
Address bus width	5
maximum clock frequency	12.024 MHz
External data bus width	8
JESD-30 code	S-PBGA-B48
JESD-609 code	e1
length	5 mm
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA48,8X8,20
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.44 mm
Maximum slew rate	30 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.5 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	10
width	5 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches	1

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Data Sheet, Rev. 2

May 2006

USS-820FD

USB 2.0 Full-Speed Device Controller

Features

■

New Features After Revision B

■

Full compliance with the

Universal Serial Bus

Specification Revision 2.0.

Backward compatible with USS-820B, USS-820C,

and USS-820D revisions.

Self-powered or bus-powered USB device. Meets

USB power specifications for bus-powered

devices.

Full-speed USB device (12 Mbits/s).

USB device controller with protocol control and

administration for up to 16 USB endpoints.

Supports control, interrupt, bulk, and isochronous

transfers for all 16 endpoints.

Programmable endpoint types, FIFO sizes, and

internal 1120-byte logical (2240-byte physical for

dual-packet mode) shared FIFO storage allow a

wide variety of configurations.

Dual-packet mode of FIFOs reduces latency.

Supports USB remote wake-up feature.

On-chip crystal oscillator allows external 12 MHz

crystal or 3 V/5 V clock source.

On-chip analog PLL creates 48 MHz clock from

internal 12 MHz clock.

Integrated USB transceivers.

5 V tolerant I/O buffers allow operation in 3 V or

5 V system environments for 0 °C to 70 °C temper-

ature range.

5 V tolerant I/O buffers allow operation in 3 V only

system environments for –20 °C to +85 °C temper-

ature range.

Implemented in Agere Systems Inc. 0.25

µm,

3 V

standard-cell library.

48-ball TFSBGAC. (Lead-free package also avail-

able. See Ordering Information on page 51.)

Evaluation kit available.

New, centralized FIFO status bits and interrupt out-

put pin reduce firmware load.

New, additional nonisochronous transmit mode

allows NAK response to cause interrupt.

Isochronous behavior enhancements simplify firm-

ware control.

Additional FIFO sizes for nonisochronous end-

points.

USB reset can be programmed to clear device

address.

USB reset output status pin.

Firmware ability to wake up and reset a suspended

device.

Lower power.

5 V supply no longer required for 5 V tolerant oper-

ation.

■

Applications

■

Suitable for peripherals with embedded micropro-

cessors.

Glueless interface to microprocessor buses.

Support of multifunction USB implementations,

such as printer/scanner and integrated multimedia

applications.

Suitable for a broad range of device class peripher-

als in the USB standard.

■

Note:

Advisories are issued as needed to update

product information. When using this data

sheet for design purposes, please contact

your Agere Systems Account Manager to

obtain the latest advisory on this product.

■

USS-820FD

USB 2.0 Full-Speed Device Controller

Data Sheet, Rev. 2

May 2006

Table of Contents

Contents

Page

Features ....................................................................................................................................................................1

New Features After Revision B .................................................................................................................................1

Applications ...............................................................................................................................................................1

Description.................................................................................................................................................................3

Serial Interface Engine........................................................................................................................................ 3

Protocol Layer ..................................................................................................................................................... 4

FIFO Control ....................................................................................................................................................... 4

FIFO Programmability ......................................................................................................................................... 4

FIFO Access ....................................................................................................................................................... 4

Transmit FIFO .............................................................................................................................................. 5

Receive FIFO ............................................................................................................................................... 6

Pin Information ......................................................................................................................................................... 7

Register Timing Characteristics................................................................................................................................. 9

Register Interface ....................................................................................................................................................11

Special Firmware Action for Shared Register Bits ............................................................................................13

Register Reads with Side Effects......................................................................................................................14

Register Descriptions ........................................................................................................................................15

Interrupts .................................................................................................................................................................40

Firmware Responsibilities for USB SETUP Commands..........................................................................................41

Other Firmware Responsibilities..............................................................................................................................42

Frame Timer Behavior.............................................................................................................................................42

Suspend and Resume Behavior..............................................................................................................................42

Hardware Suspend Detect ................................................................................................................................43

Firmware Suspend Initiate ................................................................................................................................43

Hardware Resume Detect/Initiate .....................................................................................................................44

Hardware Resume Sequence ...........................................................................................................................44

Firmware Resume Sequence ...........................................................................................................................44

Special Suspend Considerations for Bus-Powered Devices.............................................................................44

Application Notes.....................................................................................................................................................46

USB Application Support Contact Information.........................................................................................................46

Absolute Maximum Ratings.....................................................................................................................................46

Electrical Characteristics .........................................................................................................................................47

dc Characteristics .............................................................................................................................................47

Power Considerations .......................................................................................................................................48

USB Transceiver Driver Characteristics............................................................................................................48

Connection Requirements ................................................................................................................................49

USB Transceiver Connection .....................................................................................................................49

Oscillator Connection Requirements ..........................................................................................................50

Outline Diagrams.....................................................................................................................................................51

48-Ball TFSBGAC (USS-820FD) ......................................................................................................................51

Ordering Information................................................................................................................................................51

Appendix A. Special Function Register Bit Names..................................................................................................52

Appendix B. USS-820FD Register Map ..................................................................................................................53

Appendix C. Changes from USS-820/USS-825 Revision B to C ............................................................................54

Appendix D. Changes from USS-820 Revision C to D............................................................................................55

Appendix E. Changes from USS-820 Revision D to FD..........................................................................................55

Agere Systems Inc.

Data Sheet, Rev. 2

May 2006

USS-820FD

USB 2.0 Full-Speed Device Controller

Description

(continued)

FIFO Access

(continued)

Transmit FIFO

The transmit FIFOs are circulating data buffers that have the following features:

■

Support up to two separate data sets of variable sizes (dual-packet mode).

Include byte counter register for storing the number of bytes in the data sets.

Protect against overwriting data in a full FIFO.

Can retransmit the current data set.

All transmit FIFOs use the same architecture (see Figure 2). The transmit FIFO and its associated logic can man-

age up to two data sets: data set 0 (ds0) and data set 1 (ds1). Since two data sets can be used in the FIFO, back-

to-back transmissions are supported. Dual-packet mode for transmit FIFOs is enabled by default. Single-packet

mode can be enforced by firmware convention (see TXFIF register bits).

The CPU writes to the FIFO location that is specified by the write pointer. After a write, the write pointer automati-

cally increments by 1. The read marker points to the first byte of data written to a data set, and the read pointer

points to the next FIFO location to be read by the USB interface. After a read, the read pointer automatically incre-

ments by 1.

When a good transmission is completed, the read marker can be advanced to the position of the read pointer to set

up for reading the next data set. When a bad transmission is completed, the read pointer can be reversed to the

position of the read marker to enable the function interface to reread the last data set for retransmission. The read

marker advance and read pointer reversal can be achieved two ways: explicitly by firmware or automatically by

hardware, as indicated by bits in the transmit FIFO control register (TXCON).

FROM CPU

WRITE POINTER

CPU

WRITES TO FIFO

DATA SET 1

SIE READS FIFO

TXDAT

READ POINTER

TO USB INTERFACE

BYTE COUNT

REGISTERS

TXCNTH

TXCNTL

DATA SET 0

REVRP

ADVRM

READ MARKER

5-5206

Figure 2. Transmit FIFO

Agere Systems Inc.

L-USS820FD-DB Related Products

	L-USS820FD-DB	USS820FD
Description	USB Bus Controller, CMOS, PBGA48, LEAD FREE, TFSBGAC-48	USB Bus Controller, CMOS, PBGA48, TFSBGAC-48
Is it lead-free?	Lead free	Contains lead
Is it Rohs certified?	conform to	incompatible
Parts packaging code	BGA	BGA
package instruction	LFBGA, BGA48,8X8,20	LFBGA, BGA48,8X8,20
Contacts	48	48
Reach Compliance Code	unknown	compliant
Address bus width	5	5
maximum clock frequency	12.024 MHz	12.024 MHz
External data bus width	8	8
JESD-30 code	S-PBGA-B48	S-PBGA-B48
JESD-609 code	e1	e0
length	5 mm	5 mm
Number of terminals	48	48
Maximum operating temperature	85 °C	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA
Encapsulate equivalent code	BGA48,8X8,20	BGA48,8X8,20
Package shape	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	260	240
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.44 mm	1.44 mm
Maximum slew rate	30 mA	30 mA
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	OTHER	OTHER
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	TIN LEAD
Terminal form	BALL	BALL
Terminal pitch	0.5 mm	0.5 mm
Terminal location	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	10	30
width	5 mm	5 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, UNIVERSAL SERIAL BUS	BUS CONTROLLER, UNIVERSAL SERIAL BUS
Base Number Matches	1	1

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