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A14V40A-PLG84C

Description
Field Programmable Gate Array, 564 CLBs, 4000 Gates, 100MHz, 564-Cell, CMOS, PQCC84, PLASTIC, MS-007-AE, LCC-84
CategoryProgrammable logic devices    Programmable logic   
File Size489KB,68 Pages
ManufacturerActel
Websitehttp://www.actel.com/
Environmental Compliance
Download Datasheet Parametric View All

A14V40A-PLG84C Overview

Field Programmable Gate Array, 564 CLBs, 4000 Gates, 100MHz, 564-Cell, CMOS, PQCC84, PLASTIC, MS-007-AE, LCC-84

A14V40A-PLG84C Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionPLASTIC, MS-007-AE, LCC-84
Reach Compliance Codecompliant
Other featuresMAX 70 I/OS
maximum clock frequency100 MHz
Combined latency of CLB-Max3.9 ns
JESD-30 codeS-PQCC-J84
JESD-609 codee3
length29.21 mm
Humidity sensitivity level3
Configurable number of logic blocks564
Equivalent number of gates4000
Number of entries140
Number of logical units564
Output times140
Number of terminals84
Maximum operating temperature70 °C
Minimum operating temperature
organize564 CLBS, 4000 GATES
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC84,1.2SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)245
power supply3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
Maximum seat height4.45 mm
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature40
width29.21 mm
Base Number Matches1
Accelerator Series FPGAs
– ACT
3 Family
Fe atur es
• Replaces up to twenty 32 macro-cell CPLDs
• Replaces up to one hundred 20-pin PAL
®
Packages
• Up to 1153 Dedicated Flip-Flops
• VQFP, TQFP, BGA, and PQFP Packages
• Nonvolatile, User Programmable
• Fully Tested Prior to Shipment
• 5.0V and 3.3V Versions
• Optimized for Logic Synthesis Methodologies
• Low-power CMOS Technology
A1415
1,500
3,750
40
15
200
104
96
264
80
100
84
100
100
108 MHz
63 MHz
110 MHz
250 MHz
250 MHz
7.5 ns
A1425
2,500
6,250
60
25
310
160
150
360
100
133
84
100, 160
100
132
108 MHz
63 MHz
110 MHz
250 MHz
250 MHz
7.5 ns
A1440
4,000
10,000
100
40
564
288
276
568
140
175
84
160
100
176
100 MHz
63 MHz
110 MHz
250 MHz
250 MHz
8.5 ns
A1460
6,000
15,000
150
60
848
432
416
768
168
207
160, 208
176
225
196
97 MHz
63 MHz
110 MHz
200 MHz
200 MHz
9.0 ns
A14100
10,000
25,000
250
100
1,377
697
680
1,153
228
257
208
313
256
93 MHz
63 MHz
105 MHz
200 MHz
200 MHz
9.5 ns
• Up to 10,000 Gate Array Equivalent Gates
(up to 25,000 equivalent PLD Gates)
• Highly Predictable Performance with 100% Automatic
Placement and Routing
• 7.5 ns Clock-to-Output Times
• Up to 250 MHz On-Chip Performance
• Up to 228 User-Programmable I/O Pins
• Four Fast, Low-Skew Clock Networks
• More than 500 Macro Functions
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages (40 gates)
20-Pin PAL Equivalent Packages (100 gates)
Logic Modules
S-Module
C-Module
Dedicated Flip-Flops
1
User I/Os (maximum)
Packages
2
(by pin count)
CPGA
PLCC
PQFP
RQFP
VQFP
TQFP
BGA
CQFP
Performance
3
(maximum, worst-case commercial)
Chip-to-Chip
4
Accumulators (16-bit)
Loadable Counter (16-bit)
Prescaled Loadable Counters (16-bit)
Datapath, Shift Registers
Clock-to-Output (pad-to-pad)
Notes:
1. One flip-flop per S-Module, two flip-flops per I/O-Module.
2. See product plan on page 1-178 for package availability.
3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.
4. Clock-to-Output + Setup
S e p t e m b e r 19 9 7
1-175
© 1997 Actel Corporation
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