Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
119- and 209-Pin BGA
Commercial Temp
Industrial Temp
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable (x36 and x72)
• Dual Cycle Deselect only (x18)
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x36/x72 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119- and 209-bump BGA package
2M x 18, 1M x 36, 512K x 72
36Mb S/DCD Sync Burst SRAMs
250 MHz–133MHz
2.5 V or 3.3 V V
DD
2.5 V or 3.3 V I/O
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS832436(B/C) and the GS832472(C) are SCD (Single
Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined
synchronous SRAMs. The GS832418(B/C) is a DCD-only
SRAM. DCD SRAMs pipeline disable commands to the same
degree as read commands. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs begin
turning off their outputs immediately after the deselect command
has been captured in the input registers. DCD RAMs hold the
deselect command for one full cycle and then begin turning off
their outputs just after the second rising edge of clock. The user
may configure the x36 or x72 versions of this SRAM for either
mode of operation using the SCD mode input.
Pipeline
3-1-1-1
3.3 V
2.5 V
Flow
Through
2-1-1-1
3.3 V
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
Curr (x18)
Curr (x36)
Curr (x72)
t
KQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
Curr (x18)
Curr (x36)
Curr (x72)
-250 -225 -200 -166 -150 -133 Unit
2.3 2.5 3.0 3.5 3.8 4.0 ns
4.0 4.4 5.0 6.0 6.6 7.5 ns
365
560
660
360
550
640
6.0
7.0
235
300
350
235
300
340
335
510
600
330
500
590
6.5
7.5
230
300
350
230
300
340
305
460
540
305
460
530
7.5
8.5
210
270
300
210
270
300
265
400
460
260
390
450
8.5
10
200
270
300
200
270
300
245
370
430
240
360
420
10
10
195
270
300
195
270
300
215
330
380
215
330
370
11
15
150
200
220
145
190
220
mA
mA
mA
mA
mA
mA
ns
ns
mA
mA
mA
mA
mA
mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
2.5 V
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Functional Description
Applications
The GS832418/36/72 is a 37,748,736-bit high performance 2-die
synchronous SRAM module with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device now
finds application in synchronous SRAM applications, ranging
from DSP main store to networking chip set support.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS832418/36/72 operates on a 2.5 V or 3.3 V power supply.
All input are 3.3 V and 2.5 V compatible. Separate output power
(V
DDQ
) pins are used to decouple output noise from the internal
circuits and are 3.3 V and 2.5 V compatible.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
Rev: 1.00 10/2001
1/46
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology).
Preliminary
GS832418(B/C)/GS832436(B/C)/GS832472(C)
GS832418/36/72 209-Bump BGA Pin Description
Pin Location
W6, V6
W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6,
U5, U4, A3, B7, A9, U9
B5
C7
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2
L11, M11, N11, P11, L10, M10, N10, P10, R10
A10, B10, C10, D10, A11, B11, C11, D11, E11
J1, H1, G1, F1, J2, H2, G2, F2, E2
W2, V2, U2, T2, W1, V1, U1, T1, R1
L11, M11, N11, P11, L10, M10, N10, P10, R10
J1, H1, G1, F1, J2, H2, G2, F2, E2
C9, B8
B3, C4
C8, B9, B4, C3
B5
C7
W10, V10, U10, T10, W11, V11, U11, T11, R11
J11, H11, G11, F11, J10, H10, G10, F10, E10
A2, B2, C2, D2, A1, B1, C1, D1, E1
L1, M1, N1, P1, L2, M2, N2, P2, R2, C8, B9,
B4, C3
B3, C4
C5, D4, D5, D8, K1, K2, K4, K8, K9, K10, K11,
T4, T5, T7, T8, U3
K3
D7
C6
A8
A4
Rev: 1.00 10/2001
Symbol
A
0
, A
1
An
A
19
A
20
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
DQ
E1
–DQ
E9
DQ
F1
–DQ
F9
DQ
G1
–DQ
G9
DQ
H1
–DQ
H9
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
DQ
C1
–DQ
C9
DQ
D1
–DQ
D9
DQ
A1
–DQ
A9
DQ
B1
–DQ
B9
B
A
, B
B
B
C
,B
D
B
E
, B
F
, B
G
,B
H
NC
NC
Type
I
I
I
I
Description
Address field LSBs and Address Counter Preset Inputs.
Address Inputs
Address Inputs (x36/x18 Versions)
Address Inputs (x18 Version)
I/O
Data Input and Output pins (x72 Version)
I/O
Data Input and Output pins (x36 Version)
I/O
I
I
I
—
—
Data Input and Output pins (x18 Version)
Byte Write Enable for DQ
A
, DQ
B
I/Os; active low
Byte Write Enable for DQ
C
, DQ
D
I/Os; active low
(x72/x36 Versions)
Byte Write Enable for DQ
E
, DQ
F
, DQ
G
, DQ
H
I/Os; active low
(x72 Version)
No Connect (x72 Version)
No Connect (x72/x36 Versions)
NC
—
No Connect (x36/x18 Versions)
NC
NC
CK
GW
E
1
E
3
E
2
5/46
—
—
I
I
I
I
I
No Connect (x18 Version)
No Connect
Clock Input Signal; active high
Global Write Enable—Writes all bytes; active low
Chip Enable; active low
Chip Enable; active low (x72/x36 Versions)
Chip Enable; active high (x72/x36 Versions)
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Microchip MCU
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