K4S643233E-SE(N)
Revision History
Revision 1.4 (November 15, 2001) -
Final
• Final specification for 2Mx32 SDRAM.
CMOS SDRAM
Revision 1.3 (October 10, 2001) -
Preliminary
• Integrated 3.0V part numbr(K4S643234E-S(T)E(N)) and 3.3V part number(K4S643232E-S(T)E(N)) to 3.0V & 3.3V part-
number(K4S643233E-S(T)E(N)).
• Deleted tCC 5ns part and 6ns part.
• Unification of tCH 3ns for -70 part and tCH 3ns for -80 part, tCH 3ns for -10 part.
• Unification of tCL 3ns for -70 part and tCL 3ns for -80 part, tCL 3ns for -10 part.
• Unification of tSS 1.75ns for -70 part and tSS 2ns for -80 part, tSS 2.5ns for -10 part.
• Changed tCDL form 2clk to 1clk and tRDL for CL1 from 1clk to 2clk.
Revision 1.2 (August 7, 2001) -
Target
• Added CAS Latency 1
Revision 1.1 (July 6, 2001)
• Added K4S643232E-T/S(E/N)50
Revision 1.0 (April 6, 2001)
Revision 0.0 (March 21, 2001)
•
•
•
•
Initial draft
Extended temperature (-25
°
c ~ 85
°
c )
3.3V Power supply (VDD &VDDQ)
Supported 90-ball FBGA as well as 86 - TSOP
-2-
Rev. 1.4 (Nov. 2001)
K4S643233E-SE(N)
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
•
•
•
•
3.0V & 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle).
CMOS SDRAM
GENERAL DESCRIPTION
The K4S643233E is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4S643233E-SE/N70
K4S643233E-SE/N80
K4S643233E-SE/N10
K4S643233E-TE/N70
K4S643233E-TE/N80
K4S643233E-TE/N10
Max Freq.
143MHz
125MHz
100MHz
143MHz
125MHz
100MHz
Interface
Package
90-Ball
FBGA
LVTTL
86
TSOP(II)
• Extended Temperature range : -25
o
C to +85
o
C.
FUNCTIONAL BLOCK DIAGRAM
• - S(T)E/N : Extended temperature (-25
o
C - 85
o
C)
I/O Control
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
-3-
Rev. 1.4 (Nov. 2001)