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SNJ54ALS112AFK

Description
J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, CC-20
Categorylogic    logic   
File Size1022KB,18 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric View All

SNJ54ALS112AFK Overview

J-K Flip-Flop, ALS Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, TTL, CQCC20, CERAMIC, CC-20

SNJ54ALS112AFK Parametric

Parameter NameAttribute value
package instructionQCCN,
Reach Compliance Codeunknown
seriesALS
JESD-30 codeS-CQCC-N20
length8.89 mm
Logic integrated circuit typeJ-K FLIP-FLOP
Number of digits2
Number of functions2
Number of terminals20
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeQCCN
Package shapeSQUARE
Package formCHIP CARRIER
propagation delay (tpd)24 ns
Filter levelMIL-PRF-38535
Maximum seat height2.03 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelMILITARY
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationQUAD
Trigger typeNEGATIVE EDGE
width8.89 mm
minfmax25 MHz
Base Number Matches1
SN54ALS112A, SN74ALS112A
DUAL J K NEGATIVE EDGE TRIGGERED FLIP FLOPS
WITH CLEAR AND PRESET
SDAS199A − APRIL 1982 − REVISED DECEMBER 1994
Fully Buffered to Offer Maximum Isolation
From External Disturbance
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
TYPICAL MAXIMUM
CLOCK
FREQUENCY
(MHz)
50
TYPICAL POWER
DISSIPATION
PER FLIP-FLOP
(mW)
6
SN54ALS112A . . . J PACKAGE
SN74ALS112A . . . D OR N PACKAGE
(TOP VIEW)
TYPE
′ALS112A
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive
(high), data at the J and K inputs meeting the
setup-time requirements is transferred to the
outputs on the negative-going edge of the clock
pulse (CLK). Clock triggering occurs at a voltage
level and is not directly related to the fall time of the
clock pulse. Following the hold-time interval, data
at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile
flip-flops can perform as toggle flip-flops by tying
J and K high.
SN54ALS112A . . . FK PACKAGE
(TOP VIEW)
1J
1PRE
NC
1Q
1Q
1K
1CLK
NC
V
CC
3
4
5
6
7
8
2 1 20 19
18
17
16
15
1CLR
2CLR
2CLK
NC
2K
2J
14
9 10 11 12 13
NC − No internal connection
The SN54ALS112A is characterized for operation over the full military temperature range of − 55°C to 125°C.
The SN74ALS112A is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
H
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
OUTPUTS
Q
H
L
H†
Q0
H
L
Toggle
Q0
Q0
Q
L
H
H†
Q0
L
H
† The output levels in this configuration may not meet the
minimum levels for VOH. Furthermore, this configuration is
nonstable; that is, it does not persist when either PRE or
CLR returns to its inactive (high) level.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1994, Texas Instruments Incorporated
POST OFFICE BOX 655303
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
DALLAS, TEXAS 75265
2Q
GND
NC
2Q
2PRE
1
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