HY29F400
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
KEY FEATURES
n
5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
n
High Performance
– Access times as fast as 45 ns
n
Low Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 30 mA typical program/erase current
– 5 µA maximum CMOS standby current
n
Compatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
n
Sector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and seven 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and seven 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
n
Erase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
GENERAL DESCRIPTION
The HY29F400 is a 4 Megabit, 5 volt only CMOS
Flash memory organized as 524,288 (512K) bytes
or 262,144 (256K) words. The device is offered in
industry-standard 44-pin PSOP and 48-pin TSOP
packages.
The HY29F400 can be programmed and erased
in-system with a single 5-volt V
CC
supply. Inter-
nally generated and regulated voltages are pro-
vided for program and erase operations, so that
the device does not require a high voltage power
supply to perform those functions. The device can
also be programmed in standard EPROM pro-
grammers. Access times as fast as 55 ns over
the full operating voltage range of 5.0 volts ± 10%
are offered for timing compatibility with the zero
wait state requirements of high speed micropro-
Revision 5.2, May 2001
n
Sector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
n
Temporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
n
Internal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
n
Internal Programming Algorithm
– Automatically programs and verifies data
at a specified address
n
Fast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 11 sec typical
n
Data# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
n
Ready/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
n
100,000 Program/Erase Cycles Minimum
n
Space Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
LOGIC DIAGRAM
18
A[17:0]
DQ[7:0]
7
CE#
OE#
WE#
RESET#
BYTE#
RY/BY#
DQ[14:8]
DQ[15]/A-1
8
HY29F400
cessors. A 55 ns version operating over 5.0 volts
± 5% is also available. To eliminate bus conten-
tion, the HY29F400 has separate chip enable
(CE#), write enable (WE#) and output enable
(OE#) controls.
The device is compatible with the JEDEC single
power-supply Flash command set standard. Com-
mands are written to the command register using
standard microprocessor write timings, from where
they are routed to an internal state-machine that
controls the erase and programming circuits.
Device programming is performed a byte or word
at a time by executing the four-cycle Program com-
mand. This initiates an internal algorithm that au-
tomatically times the program pulse widths and
verifies proper cell margin.
The HY29F400’s sector erase architecture allows
any number of array sectors to be erased and re-
programmed without affecting the data contents
of other sectors. Device erasure is initiated by
executing the Erase command. This initiates an
internal algorithm that automatically preprograms
the array (if it is not already programmed) before
executing the erase operation. During erase
cycles, the device automatically times the erase
pulse widths and verifies proper cell margin.
To protect data in the device from accidental or
unauthorized attempts to program or erase the
BLOCK DIAGRAM
device while it is in the system (e.g., by a virus),
the device has a Sector Protect function which
hardware write protects selected sectors. The
sector protect and unprotect features can be en-
abled in a PROM programmer. Temporary Sec-
tor Unprotect, which requires a high voltage, al-
lows in-system erasure and code changes in pre-
viously protected sectors.
Erase Suspend enables the user to put erase on
hold for any period of time to read data from, or
program data to, any sector that is not selected
for erasure. True background erase can thus be
achieved. The device is fully erased when shipped
from the factory.
Addresses and data needed for the programming
and erase operations are internally latched during
write cycles, and the host system can detect
completion of a program or erase operation by
observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.
Reading data from the device is similar to reading
from SRAM or EPROM devices. Hardware data
protection measures include a low V
CC
detector
that automatically inhibits write operations during
power transitions.
The host can place the device into the standby
mode. Power consumption is greatly reduced in
this mode.
DQ[15:0]
A[17:0], A-1
STATE
CONTROL
DQ[15:0]
WE#
CE#
OE#
BYTE#
RESET#
RY/BY#
PROGRAM
VOLTAGE
GENERATOR
COMMAND
REGISTER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
I/O CONTROL
I/O BUFFERS
DATA LATCH
V
C C
DETECTOR
TIMER
A[17:0], A-1
ADDRESS LATCH
Y-DECODER
Y-GATING
X-DECODER
4 Mb FLASH
MEMORY
ARRAY
2
Rev. 5.2/May 01
HY29F400
PIN CONFIGURATIONS
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
V
SS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
PSOP44
Standard
TSOP48
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reverse
TSOP48
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
CONVENTIONS
Unless otherwise noted, a positive logic (active
High) convention is assumed throughout this docu-
ment, whereby the presence at a pin of a higher,
more positive voltage (nominally 5VDC) causes
assertion of the signal. A ‘#’ symbol following the
signal name, e.g., RESET#, indicates that the sig-
nal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered
bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of
bits may also be shown collectively, e.g., as
DQ[7:0].
The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, .
. . , E, F) indicates a number expressed in hexadeci-
mal notation. The designation 0bXXXX indicates a
number expressed in binary notation (X = 0, 1).
3
Rev. 5.2/May 01
HY29F400
SIGNAL DESCRIPTIONS
Name
A[17:0]
Type
Inputs
Description
Address, active High.
In Word mode, these 18 inputs select one of 262,144
(256K) words within the array for read or write operations. In Byte mode, these
inputs are combined with the DQ15/A-1 input (LSB) to select one of 524,288
(512K) bytes within the array for read or write operations.
DQ[15]/A[-1],
DQ[14:0]
BY TE#
CE#
Data Bus, active High
. In Word mode, these pins provide a 16-bit data path
Inputs/Outputs for read and write operations. In Byte mode, DQ[7:0] provide an 8-bit data path
Tri-state
and DQ[15]/A[-1] is used as the LSB of the 19-bit byte address input. DQ[14:8]
are unused and remain tri-stated in Byte mode.
Input
Input
Byte Mode, active Low.
Controls the Byte/Word configuration of the device.
Low selects Byte mode, High selects Word mode.
Chip Enable, active Low.
This input must be asserted to read data from or
write data to the HY 29F400. When High, the data bus is tri-stated and the device
is placed in the Standby mode.
Output Enable, active Low
. This input must be asserted for read operations
and negated for write operations. BY TE# determines whether a byte or a word
is read during the read operation. When High, data outputs from the device are
disabled and the data bus pins are placed in the high impedance state.
W r it e E n a b le , a c t iv e L o w.
Co nt r o ls w r it ing o f c o mma nd s o r c o mma nd
sequences in order to program data or erase sectors of the memory array. A
write operation takes place when WE# is asserted while CE# is Low and OE#
is High. BY TE# determines whether a byte or a word is written during the write
operation.
Hardware Reset, active Low.
Provides a hardware method of resetting the
HY 29F400 to the read array state. When the device is reset, it immediately
terminates any operation in progress. The data bus is tri-stated and all read/write
commands are ignored while the input is asserted. While RESET# is asserted,
the device will be in the Standby mode.
Re a dy / Bus y St a t us .
I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in
progress or has been completed. RY /BY # is valid after the rising edge of the
final WE# pulse of a command sequence. It remains Low while the device is
actively programming data or erasing, and goes High when it is ready to read
array data.
5-volt power supply.
Power and signal ground.
OE#
Input
WE#
Input
RESET#
Input
RY /BY #
Output
Open Drain
--
--
V
CC
V
SS
4
Rev. 5.2/May 01
HY29F400
MEMORY ARRAY ORGANIZATION
The 4 Mbit Flash memory array is organized into
11 blocks called
sectors
(S0, S1, . . . , S10). A
sector is the smallest unit that can be erased and
which can be protected to prevent accidental or
unauthorized erasure. See the ‘Bus Operations’
and ‘Command Definitions’ sections of this docu-
ment for additional information on these functions.
In the HY29F400, four of the sectors, which com-
prise the
boot block,
vary in size from 8 to 32
Kbytes (4 to 16 Kwords), while the remaining
seven sectors are uniformly sized at 64 Kbytes
(32 Kwords). The boot block can be located at
the bottom of the address range (HY29F400B) or
at the top of the address range (HY29F400T).
Table 1 defines the sector addresses and corre-
sponding address ranges for the top and bottom
boot block versions of the HY29F400.
BUS OPERATIONS
Device bus operations are initiated through the
internal command register, which consists of sets
of latches that store the commands, along with
the address and data information, if any, needed
to execute the specific command. The command
register itself does not occupy any addressable
memory location. The contents of the command
register serve as inputs to an internal state ma-
chine whose outputs control the operation of the
device. Table 2 lists the normal bus operations,
Table 1. HY29F400 Memory Array Organization
Device Sector
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
Sector Address
Size
(KB/KW) A[17] A[16] A[15] A[14] A[13] A[12]
64/32
64/32
64/32
64/32
64/32
64/32
64/32
32/16
8/4
8/4
16/8
16/8
8/4
8/4
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
0
1
1
1
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
0
1
X
X
X
X
X
X
X
X
Byte Mode
Address Range
2
0x00000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
0x40000 - 0x4FFFF
0x50000 - 0x5FFFF
0x60000 - 0x6FFFF
0x70000 - 0x77FFF
0x78000 - 0x79FFF
0x7A000 - 0x7BFFF
0x7C000 - 0x7FFFF
0x00000 - 0x03FFF
0x04000 - 0x05FFF
0x06000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x1FFFF
0x20000 - 0x2FFFF
0x30000 - 0x3FFFF
0x40000 - 0x4FFFF
0x50000 - 0x5FFFF
0x60000 - 0x6FFFF
0x70000 - 0x7FFFF
Word Mode
Address Range
3
0x00000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3BFFF
0x3C000 - 0x3CFFF
0x3D000 - 0x3DFFF
0x3E000 - 0x3FFFF
0x00000 - 0x01FFF
0x02000 - 0x02FFF
0x03000 - 0x03FFF
0x04000 - 0x07FFF
0x08000 - 0x0FFFF
0x10000 - 0x17FFF
0x18000 - 0x1FFFF
0x20000 - 0x27FFF
0x28000 - 0x2FFFF
0x30000 - 0x37FFF
0x38000 - 0x3FFFF
Notes:
1. X indicates Don’t Care.
2. Address in Byte Mode is A[17:-1].
3. Address in Word Mode is A[17:0].
Rev. 5.2/May 01
HY29F400B - Bottom Boot Block
HY29F400T - Top Boot Block
5
京公网安备 11010802033920号
EEWORLD
