5/0251
ADVANCE INFORMATION
CY7C4808V25
CY7C4806V25
CY7C4804V25
2.5V 4K/16K/64K x 80 Unidirectional
Synchronous FIFO w/Bus Matching
Features
• High-speed, low-power, unidirectional, first-in first-out
(FIFO) memories w/bus matching capabilities
• 64K x 80 (CY7C4808V25)
• 16K x 80 (CY7C4806V25)
• 4K x 80 (CY7C4804V25)
• 2.5V ± 125 mV power supply
• Fabricated using Cypress 0.21-micron CMOS Technol-
ogy for optimum speed/power
• Individual clock frequency up to 200 MHz (5 ns
read/write cycle times)
• High-speed access with t
A
= 3.5
• Bus matching on both ports: x80, x40, x20, x10
• Free-running CLKA and CLKB. Clocks may be asyn-
chronous or coincident
• CY standard or First-Word Fall-Through modes
• Serial and parallel programming of Almost Empty/Full
flags, each with 3 default values (8, 16, 64)
• Master and Partial reset capability
• Retransmit capability
• All I/Os are 1.5V HSTL
• Big or Little Endian format on Port B
• 288 FBGA 19 mm x 19 mm (1.0-mm ball pitch) packaging
• Width and depth expansion capability
Preliminary Top Level Block Diagram
CLKA
CSA
ENA
MBA
SIZE1A
SIZE2A
MBF
IM
CLKB
Port A
Control
Logic
MailBox
Register
Port B
Control
Logic
CSB
ENB
MBB
BE/FWFT
SIZE1B
SIZE2B
RT/SPM
OE
A
79–0
80
Write
Pointer
Read
Pointer
Bus Matching Output Register
Bus Matching Input Register
Write Data Path Logic
Read Data Path Logic
4K/16K/64K
x80
Dual Ported
Memory
80
B
79–0
4K/16K/64K
x80
Dual Ported
Memory
MRS
PRS
FIFO
Reset
Logic
Status
Flag Logic
FF/IR
AF
EF/OR
AE
TDO
FS0/SD
FS1/SEN
Programmable Flag
Offset Registers
JTAG/BIST Controller
TDI
TCK
TMS
TRST
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
December 16, 1999
ADVANCE INFORMATION
Functional Description
The CY7C480XV25 family of FIFOs is high-speed, low-power,
CMOS Synchronous (clocked) FIFO memories, meaning each
port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of the
clock on either port by the enable signal. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enable for each port is arranged to provide
a simple unidirectional interface between microprocessors
and/or buses with synchronous control.
Two kinds of reset are available on the CY7C480XV25: Master
Reset and Partial Reset. Master Reset initializes the read and
write pointers to the first location of the memory array, config-
ures the FIFO for Big Endian or Little Endian byte arrange-
ment, selects the CY standard or First-Word Fall-Through
(FWFT) mode, and determines the configuration of the pro-
grammable flags. The flags can be programmed either in serial
mode or in parallel mode. The FIFO also comes with three
possible default flag offset settings: 8, 16, or 64.
Partial Reset also sets the read and write pointers to the first
location of the memory. Unlike Master Reset, any settings ex-
isting prior to Partial Reset (i.e., programming method and par-
tial flag default offsets) are retained. Partial Reset is useful
since it permits flushing of the FIFO memory without changing
any configuration settings.
The CY7C480XV25 have two modes of operation: CY Stan-
dard Mode or First-Word Fall-Through Mode (FWFT). In the
CY Standard Mode, the first word written to an empty FIFO is
deposited into the memory array. A read operation is required
to access that word (along with all other words residing in
memory). In the FWFT Mode, the first long-word (80-bit-wide)
written to an empty FIFO appears automatically on the out-
puts, and no read operation is required. Nevertheless, access-
CY7C4808V25
CY7C4806V25
CY7C4804V25
ing subsequent words does necessitate a formal read request.
FWFT mode is primarily used for cascading 2 or more FIFOs.
The FIFO has an EF_OR flag on port B and FF_IR flag on Port
A. The EF and FF functions are selected in the CY Standard
Mode. EF indicates whether or not the FIFO memory is empty.
FF shows whether or not the memory is full. The IR and OR
functions are selected in the First-Word Fall-Through mode. IR
indicates whether or not the FIFO has memory locations avail-
able. OR shows whether the FIFO has data available for read-
ing or not. It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Empty flag (AE) and a
programmable Almost Full flag (AF). AE indicates the number
of words left in the FIFO memory is at the user-defined
amount. AF indicates the number of words written into the
FIFO memory has achieved a predetermined amount.
FF_IR and AF flags are synchronized to port A clock that
writes data into its array. EF_OR and AE flags are synchro-
nized to Port B clock that reads data from its array. Program-
mable offsets for AE and AF are loaded in parallel via Port A
or in serial via the SD input. The Serial Programming Mode pin
(SPM) makes this selection. Three default offsets setting are
also provided. The AE threshold can be set at 8, 16 or 64
locations from the empty boundary and AF threshold can be
set at 8, 16, or 64 locations from the full boundary. All these
choices are made using the FS0 and FS1 inputs during Master
Reset.
Two or more devices may be used in parallel to create wider
data paths. If, at any time, the FIFO is not actively performing
a function, the chip will automatically power down. During the
Power-Down state, supply current consumption (I
CC
) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the Power-Down state.
The CY7C480XV25 FIFOs are characterized for operation
from 0°C to 70°C commercial, and from –40°C to 85°C indus-
trial.
Selection Guide
CY7C480XV25-200
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
200
3.5
5
0.6
0.6
3.5
CY7C480XV25-166
166
4
6
0.6
0.6
4
CY7C4808V25
Density
Package
64K x 80
288 FBGA
CY7C4806V25
16K x 80
288 FBGA
CY7C4804V25
4K x 80
288 FBGA
2
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