AT25F1024Y4-10YI-2.7 datasheet, PDF

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AT25F1024Y4-10YI-2.7: DescriptionFlash, 128KX8, PDSO8, SAP-8; Categorystorage storage; File Size263KB，18 Pages; ManufacturerAtmel (Microchip)

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AT25F1024Y4-10YI-2.7 Overview

Flash, 128KX8, PDSO8, SAP-8

AT25F1024Y4-10YI-2.7 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	HVSON, SOLCC8,.25
Reach Compliance Code	unknown
Maximum clock frequency (fCLK)	20 MHz
Durability	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-N8
JESD-609 code	e0
length	6 mm
memory density	1048576 bit
Memory IC Type	FLASH
memory width	8
Humidity sensitivity level	3
Number of functions	1
Number of terminals	8
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	HVSON
Encapsulate equivalent code	SOLCC8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/Serial	SERIAL
power supply	3/3.3 V
Programming voltage	2.7 V
Certification status	Not Qualified
Maximum seat height	0.9 mm
Serial bus type	SPI
Maximum standby current	0.00001 A
Maximum slew rate	0.03 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
type	NOR TYPE
width	4.9 mm
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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Features

•

Serial Peripheral Interface (SPI) Compatible

Supports SPI Modes 0 (0,0) and 3 (1,1)

20 MHz Clock Rate

Byte Mode and 256-byte Page Mode for Program Operations

Sector Architecture:

– Two Sectors with 32K Bytes Each (512K)

– Four Sectors with 32K Bytes Each (1M)

– 128 Pages per Sector

Product Identification Mode

Low-voltage Operation

– 2.7 (V

= 2.7V to 3.6V)

Sector Write Protection

Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

Self-timed Program Cycle (60 µs/Byte Typical)

Self-timed Sector Erase Cycle (1 second/Sector Typical)

Single Cycle Reprogramming (Erase and Program) for Status Register

High Reliability

– Endurance: 10,000 Write Cycles Typical

Lead-free Devices Available

8-lead JEDEC SOIC and 8-lead SAP Packages

•

SPI Serial

Memory

512K (65,536 x 8)

1M (131,072 x 8)

Description

The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash

memory organized as 65,536/131,072 words of 8 bits each. The device is optimized

for use in many industrial and commercial applications where low-power and low-volt-

age operation are essential. The AT25F512/1024 is available in a space-saving 8-lead

JEDEC SOIC and 8-lead SAP packages.

The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a

3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and

Serial Clock (SCK). All write cycles are completely self-timed.

BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or

entire memory array (512K) is enabled by programming the status register. Separate

write enable and write disable instructions are provided for additional data protection.

Hardware data protection is provided via the WP pin to protect against inadvertent

write attempts to the status register. The HOLD pin may be used to suspend any serial

communication without resetting the serial sequence.

AT25F512

AT25F1024

Pin Configurations

Pin Name

SCK

GND

VCC

HOLD

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

Write Protect

Suspends Serial Input

VCC

HOLD

SCK

GND

8-lead SOIC

VCC

HOLD

SCK

8-lead SAP

GND

Bottom View

Rev. 1440P–SEEPR–6/04

AT25F512/1024

Serial Interface

Description

MASTER:

The device that generates the serial clock.

SLAVE:

Because the Serial Clock pin (SCK) is always an input, the AT25F512/1024

always operates as a slave.

TRANSMITTER/RECEIVER:

The AT25F512/1024 has separate pins designated for

data transmission (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will be

received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25F512/1024, and the serial output pin (SO) will remain in a high impedance state

until the falling edge of CS is detected again. This will reinitialize the serial

communication.

CHIP SELECT:

The AT25F512/1024 is selected when the CS pin is low. When the

device is not selected, data will not be accepted via the SI pin, and the serial output pin

(SO) will remain in a high impedance state.

HOLD:

The HOLD pin is used in conjunction with the CS pin to select the

AT25F512/1024. When the device is selected and a serial sequence is underway,

HOLD can be used to pause the serial communication with the master device without

resetting the serial sequence. To pause, the HOLD pin must be brought low while the

SCK pin is low. To resume serial communication, the HOLD pin is brought high while the

SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored

while the SO pin is in the high impedance state.

WRITE PROTECT:

The 25F512/1024 has a write lockout feature that can be activated

by asserting the write protect pin (WP). When the lockout feature is activated, locked-out

sectors will be READ only. The write protect pin will allow normal read/write operations

when held high. When the WP is brought low and WPEN bit is “1”, all write operations to

the status register are inhibited. WP going low while CS is still low will interrupt a write to

the status register. If the internal status register write cycle has already been initiated,

WP going low will have no effect on any write operation to the status register. The WP

pin function is blocked when the WPEN bit in the status register is “0”. This will allow the

user to install the AT25F512/1024 in a system with the WP pin tied to ground and still be

able to write to the status register. All WP pin functions are enabled when the WPEN bit

is set to “1”.

1440P–SEEPR–6/04

AT25F1024Y4-10YI-2.7 Related Products

	AT25F1024Y4-10YI-2.7	AT25F512Y4-10YI-2.7
Description	Flash, 128KX8, PDSO8, SAP-8	Flash, 64KX8, PDSO8, SAP-8
Is it Rohs certified?	incompatible	incompatible
package instruction	HVSON, SOLCC8,.25	HVSON, SOLCC8,.25
Reach Compliance Code	unknown	unknown
Maximum clock frequency (fCLK)	20 MHz	20 MHz
Durability	10000 Write/Erase Cycles	10000 Write/Erase Cycles
JESD-30 code	R-PDSO-N8	R-PDSO-N8
JESD-609 code	e0	e0
length	6 mm	6 mm
memory density	1048576 bit	524288 bit
Memory IC Type	FLASH	FLASH
memory width	8	8
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	8	8
word count	131072 words	65536 words
character code	128000	64000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
organize	128KX8	64KX8
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HVSON	HVSON
Encapsulate equivalent code	SOLCC8,.25	SOLCC8,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE	SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Parallel/Serial	SERIAL	SERIAL
power supply	3/3.3 V	3/3.3 V
Programming voltage	2.7 V	2.7 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	0.9 mm	0.9 mm
Serial bus type	SPI	SPI
Maximum standby current	0.00001 A	0.00001 A
Maximum slew rate	0.03 mA	0.03 mA
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
type	NOR TYPE	NOR TYPE
width	4.9 mm	4.9 mm
write protect	HARDWARE/SOFTWARE	HARDWARE/SOFTWARE

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