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MAX 7000A
®
Includes
MAX 7000AE
Programmable Logic
Device
Data Sheet
September 2002, ver. 4.2
Features...
■
■
■
■
■
■
■
High-performance 3.3-V EEPROM-based programmable logic
devices (PLDs) built on second-generation Multiple Array MatriX
(MAX
®
) architecture (see
Table 1)
3.3-V in-system programmability (ISP) through the built-in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
–
MAX 7000AE device in-system programmability (ISP) circuitry
compliant with IEEE Std. 1532
–
EPM7128A and EPM7256A device ISP circuitry compatible with
IEEE Std. 1532
Built-in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1
Supports JEDEC Jam Standard Test and Programming Language
(STAPL) JESD-71
Enhanced ISP features
–
Enhanced ISP algorithm for faster programming (excluding
EPM7128A and EPM7256A devices)
–
ISP_Done bit to ensure complete programming (excluding
EPM7128A and EPM7256A devices)
–
Pull-up resistor on I/O pins during in-system programming
Pin-compatible with the popular 5.0-V MAX 7000S devices
High-density PLDs ranging from 600 to 10,000 usable gates
f
For information on in-system programmable 5.0-V MAX 7000 or 2.5-V
MAX 7000B devices, see the
MAX 7000 Programmable Logic Device Family
Data Sheet
or the
MAX 7000B Programmable Logic Device Family Data Sheet.
Table 1. MAX 7000A Device Features
Feature
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
PD
(ns)
t
SU
(ns)
t
FSU
(ns)
t
CO1
(ns)
f
CNT
(MHz)
Altera Corporation
DS-M7000A-4.2
EPM7032AE
600
32
2
36
4.5
2.9
2.5
3.0
227.3
EPM7064AE
1,250
64
4
68
4.5
2.8
2.5
3.1
222.2
EPM7128AE
2,500
128
8
100
5.0
3.3
2.5
3.4
192.3
EPM7256AE
5,000
256
16
164
5.5
3.9
2.5
3.5
172.4
EPM7512AE
10,000
512
32
212
7.5
5.6
3.0
4.7
116.3
1
MAX 7000A Programmable Logic Device Data Sheet
...and More
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
4.5-ns pin-to-pin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
TM
I/O interface enables device core to run at 3.3 V, while
I/O pins are compatible with 5.0-V, 3.3-V, and 2.5-V logic levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), ball-grid array (BGA), space-
saving FineLine BGA
TM
, and plastic J-lead chip carrier (PLCC)
packages
Supports hot-socketing in MAX 7000AE devices
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
PCI-compatible
Bus-friendly architecture, including programmable slew-rate control
Open-drain output option
Programmable macrocell registers with individual clear, preset,
clock, and clock enable controls
Programmable power-up states for macrocell registers in
MAX 7000AE devices
Programmable power-saving mode for 50% or greater power
reduction in each macrocell
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
Programmable security bit for protection of proprietary designs
6 to 10 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Fast input setup times provided by a dedicated path from I/O pin to
macrocell registers
Programmable output slew-rate control
Programmable ground pins
Software design support and automatic place-and-route provided by
Altera’s development systems for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Altera’s Master Programming Unit
(MPU), MasterBlaster
TM
serial/universal serial bus (USB)
communications cable, ByteBlasterMV
TM
parallel port download
cable, and BitBlaster
TM
serial download cable, as well as
programming hardware from third-party manufacturers and any
Jam
TM
STAPL File (.jam), Jam Byte-Code File (.jbc), or Serial Vector
Format File- (.svf) capable in-circuit tester
2
Altera Corporation
MAX 7000A Programmable Logic Device Data Sheet
General
Description
MAX 7000A (including MAX 7000AE) devices are high-density, high-
performance devices based on Altera’s second-generation MAX
architecture. Fabricated with advanced CMOS technology, the EEPROM-
based MAX 7000A devices operate with a 3.3-V supply voltage and
provide 600 to 10,000 usable gates, ISP, pin-to-pin delays as fast as 4.5 ns,
and counter speeds of up to 227.3 MHz. MAX 7000A devices in the -4, -5,
-6, -7, and some -10 speed grades are compatible with the timing
requirements for 33 MHz operation of the PCI Special Interest Group (PCI
SIG)
PCI Local Bus Specification, Revision 2.2.
See
Table 2.
Table 2. MAX 7000A Speed Grades
Device
-4
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Speed Grade
-5
-6
-7
v
v
v
v
v
v
v
v
v
v
v
-10
v
v
v
v
v
v
v
v
v
v
-12
v
v
The MAX 7000A architecture supports 100% transistor-to-transistor logic
(TTL) emulation and high-density integration of SSI, MSI, and LSI logic
functions. It easily integrates multiple devices including PALs, GALs, and
22V10s devices. MAX 7000A devices are available in a wide range of
packages, including PLCC, BGA, FineLine BGA, Ultra FineLine BGA,
PQFP, and TQFP packages. See
Table 3
and
Table 4.
Altera Corporation
3
MAX 7000A Programmable Logic Device Data Sheet
Table 3. MAX 7000A Maximum User I/O Pins
Device
44-Pin
PLCC
44-Pin
TQFP
49-Pin
Ultra
FineLine
BGA
(2)
41
Note (1)
84-Pin
PLCC
100-Pin 100-Pin
TQFP FineLine
BGA
(3)
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
36
36
36
36
68
68
68
84
84
84
84
84
68
84
84
Table 4. MAX 7000A Maximum User I/O Pins
Device
144-Pin
TQFP
169-Pin
Ultra
FineLine
BGA
(2)
Note (1)
256-Pin
BGA
256-Pin
FineLine
BGA
(3)
208-Pin
PQFP
EPM7032AE
EPM7064AE
EPM7128A
EPM7128AE
EPM7256A
EPM7256AE
EPM7512AE
Notes to tables:
(1)
(2)
When the IEEE Std. 1149.1 (JTAG) interface is used for in-system programming or
boundary-scan testing, four I/O pins become JTAG pins.
All Ultra FineLine BGA packages are footprint-compatible via the SameFrame
TM
feature. Therefore, designers can design a board to support a variety of devices,
providing a flexible migration path across densities and pin counts. Device
migration is fully supported by Altera development tools. See
“SameFrame Pin-
Outs” on page 15
for more details.
All FineLine BGA packages are footprint-compatible via the SameFrame feature.
Therefore, designers can design a board to support a variety of devices, providing
a flexible migration path across densities and pin counts. Device migration is fully
supported by Altera development tools. See
“SameFrame Pin-Outs” on page 15
for
more details.
100
100
120
120
120
100
164
164
176
212
100
100
164
164
212
(3)
4
Altera Corporation
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