White Electronic Designs
W3HG128M72AEF-Fx
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM FBDIMM, ECC
FEATURES
240-pin DDR2 fully buffered, dual in-line memory
module (FBDIMM) with ECC to detect and report
channel errors to the host memory controller.
Fast DDR2 DRAM data transfer rates: PC2-6400*,
PC2-5300, and PC2-4300
3.2 Gb/s and 4.0 Gb link transfer rates
High speed differential point-to-point link between
host memory controller and the AMB using serial,
dual-simplex bit lanes
• 10-pair southbound (data path to FBDIMM)
• 14-pair northbound (data path to FBDIMM)
Fault tolerant; can work around a bad bit lane in
each direction
High density scaling with up to 8 dual-rank modules
(288 DDR2 SDRAM devices) per channel
SMBus interface to AMB for configuration register
access.
In-band and out-bank command access
Deterministic protocol
• Enables memory controller to optimize DRAM
access for maximum performance
• Delivers precise control and repeatable memory
behavior
Automatic DDR2 SDRAM bus and channel
calibration
Transmitter de-emphasis to reduce ISI
MBIST and IBIST test functions
Transparent mode for DDR2 SDRAM test support
V
CC
= V
CCQ
= +1.8V for DDR2 SDRAM
V
REF
= 0.9V SDRAM C/A termination
V
CC
= 1.5V for advanced memory buffer (AMB)
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual rank
RoHS
DESCRIPTION
The W3HG128M72AEF is a 128Mx72 fully buffered 240-
pin Double Data Rate 2 SDRAM memory module based
on 512Mb DDR2 SDRAM components. The module
consists of eighteen 128Mx4, in FBGA package and a
AMB mounted on a 240 pin FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
PERFORMANCE PARAMETERS
Speed Grade
665
534
Module Bandwidth
PC2-5300
PC2-4200
Peak Channel Throughput
8.0 GB/s
6.4 GB/s
Link Transfer Rate
4.0 GT/s
3.2 GT/s
Latency (CL-t
RCD
-t
RP
)
5-5-5
4-4-4
* Consult factory for availability
Note: JEDEC has not yet adopted a
fi
nal FBDIMM standard
September 2007
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
PIN ASSIGNMENT – 240 PIN FBDIMM
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SYMBOL
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID1
RESET#
V
SS
RFU
2
RFU
2
V
SS
PN0
PN0#
V
SS
PN1
PN1#
V
SS
PN2
PN2#
V
SS
PN3
PN3#
V
SS
PN4
PN4#
V
SS
PN5
PN5#
V
SS
PN13
PN13#
V
SS
V
SS
RFU
RFU
V
SS
V
SS
PN12
PN12#
V
SS
PN6
PN6#
V
SS
PN7
PN7#
V
SS
PN8
PN8#
V
SS
PN9
PIN
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
SYMBOL
PN9#
V
SS
PN10
PN10#
V
SS
PN11
PN11#
V
SS
V
SS
PS0
PS0#
V
SS
PS1
PS1#
V
SS
PS2
PS2#
V
SS
PS3
PS3#
V
SS
PS4
PS4#
V
SS
V
SS
RFU
1
RFU
1
V
SS
V
SS
PS9
PS9#
V
SS
PS5
PS5#
V
SS
PS6
PS6#
V
SS
PS7
PS7#
V
SS
PS8
PS8#
V
SS
RFU
2
RFU
2
V
SS
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
SA2
SDA
SCL
PIN
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
SYMBOL
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
DD
V
SS
V
CC
V
CC
V
SS
V
CC
V
CC
V
SS
V
TT
VID0
DNU/M_Test
V
SS
RFU
2
RFU
2
V
SS
SN0
SN0#
V
SS
SN1
SN1#
V
SS
SN2
SN2#
V
SS
SN3
SN3#
V
SS
SN4
SN4#
V
SS
SN5
SN5#
V
SS
SN13
SN13#
V
SS
V
SS
RFU
1
RFU
1
V
SS
V
SS
SN12
SN12#
V
SS
SN6
SN6#
V
SS
SN7
SN7#
V
SS
SN8
SN8#
V
SS
SN9
PIN
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
SYMBOL
SN9#
V
SS
SN10
SN10#
V
SS
SN11
SN11#
V
SS
V
SS
SS0
SS0#
V
SS
SS1
SS1#
V
SS
SS2
SS2#
V
SS
SS3
SS3#
V
SS
SS4
SS4#
V
SS
V
SS
RFU
1
RFU
1
V
SS
V
SS
SS9
SS9#
V
SS
SS5
SS5#
V
SS
SS6
SS6#
V
SS
SS7
SS7#
V
SS
SS8
SS8#
V
SS
RFU
2
RFU
2
V
SS
SCK
SCK#
V
SS
V
DD
V
DD
V
DD
V
SS
V
DD
V
DD
V
TT
V
CC
SPD
SA0
SA1
2
W3HG128M72AEF-Fx
ADVANCED
PIN NAMES
Symbol
SCK
SCK#
PN0-PN13
PN0#-PN13#
PS0-PS9
PS0#-PS9#
SN0-SN13
SN0#-SN13#
SS0-SS9
SS0#-SS9#
SCL
SDA
SA0-SA2
Descriptions
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
SPD Address Inputs, also used to select the
FBDIMM number in the AMB
Voltage ID: These pins must be
unconnected for DDR2-based FBDIMMs.
VID0 is V
DD
value: OPEN=1.8V,
GND=1.5V;VID1 is VCC value: OPEN=1.5V,
GND=1.2V
AMB reset signal
Reserved for Future Use
AMB Core Power and AMB Channel
Interface Power (1.5V)
DRAM Power and AMB DRAM I/O Power
(1.8V)
DRAM Address/Command/Clock
Termination Power (V
DD/2
)
SPD Power
Ground
Do Not Use
VID0-VID1
RESET#
RFU
V
CC
V
DD
V
TT
V
CC
SPD
V
SS
DNU/M_TEST
Note:
1. These pin positions are reserved for forwarded clocks to be used in
future module implemenations
2. These pin positions are reserved for future architechture
fl
exibility.
3. The following signals are CRC bits and thus appear out of the
normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#,
PS9/PS9#, SS9/SS9#.
4. RFU = Reserved Future Use.
September 2007
Rev. 3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
V
SS
CS0#
CS1#
DQS0
DQS0#
DM
CS#
DQS DQS#
W3HG128M72AEF-Fx
ADVANCED
DQS9
DQS9
DM
CS#
DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7#
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DQ60
DQ61
DQ62
DQ63
DQS17
DQS17#
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
DM
DM
CS#
DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
V
TT
Out to Ctrl
PN0-PN13
PN0#-PN13#
PS0-PS9
In from Ctrl
PS0#-PS9#
DQ0-DQ63
DQS0-DQS17
DQS0#-DQS17#
CB0 -CB7
SCL
SDA
SA0-SA2
SCK, SCK#
RESET#
A
M
B
SN0-SN13
SN0#-SN13#
SS0-SS9
SS0#-SS9#
A0-A15
RAS#, CAS#
WE#, ODT0
CS0#, CS1#
CKE0, CKE1
CK0, CK0#
CK1, CK1#
In from adj. FBDIMM
Out to adj. FBDIMM
Terminators
V
CCSPD
V
CC
V
DD
V
REF
Serial PD, AMB
AMB
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
Serial PD, AMB
Data Input/Output
signals to DDR2 Channel
Command, Address and
Clock signals to DDR2 Channel
V
SS
Command, address and clock line terminations:
22
RAS#, CAS#, A0–A15,
V
TT
ODT0, WE#, BA0–BA2
30
CK0, CK0#, CK1, CK1#,
CS0, CS1#,
CKE0, CKE1
39
SCL
Serial PD
WP A0
A1
A2
SA0 SA1 SA2
SDA
V
TT
V
TT
September 2007
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
GENERAL DESCRIPTION
WEDC FBDIMM is a high-bandwidth, large-capacity-
channel solution that has narrow host interface.
FBDIMMs used DDR2 SDRAM devices isolated from
the channel behind a buffer on the FBDIMM. Memory
device capacity remains high and total memory capacity
scales with DDR2 SDRAM bit density.
As shown in Figure 1, the FBDIMM channel provides a
communication path from a host controller to an array of
DDR2 SDRAM devices, with the DDR2 SDRAM devices
buffered behind an AMB device. The physical isolation
of the DDR2 SDRAM devices from the channel enables
the flexibility to enhance the communication path to
significantly increase the reliability and availability of the
memory subsystem.
WEDC FBDIMM features a novel architecture, including
the AMB that isolates the DDR2 SDRAM devices from
the channel. This single-chip AMB component, located
W3HG128M72AEF-Fx
ADVANCED*
in the center of each FBDIMM, acts as a repeater
and buffer for all signals and commands exchanged
between the host controller and the DDR2 SDRAM
devices, including data input and output. The AMB
communicates with the host controller and adjacent
FBDIMMs on a system board using an industry-
standard, high-speed, differential, point-to-point,
interface at 1.5V.
The AMB also allows buffering of memory traffic to
support large memory capacities. All memory control for
the DDR2 SDRAM devices resides in the host, including
memory request initiation, timing, refresh, scrubbing,
sparing, configuration access, and power management.
The AMB interface is responsible for handling channel
and memory requests to and from the local FBDIMM
and for forwarding requests to other FBDIMMs on the
memory channel.
FIGURE 1: FBDIMM Solution Block Diagram
DDR2 connector with unique key
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
Commodity
DDR2 SDRAM
Devices
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
10
Up to 8 modules
AMB
AMB
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
AMB
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
• • •
AMB
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
Memory
Controller
14
DDR2
Component
DDR2
Component
DDR2
Component
SMBus
DDR2
Component
CLK
Source
Common clock source
SMbus access
to buffer registers
September 2007
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL DESCRIPTION
ADVANCED MEMORY BUFFER (AMB)
The AMB reference design complies with the "FBDIMM
Architecture and Protocol Specification" (JEDEC
standards, pending). It is expected that there will be
multiple vendors for the AMB which will offer at least
the minimum functionally as set forth in the industry
specification. To achieve optimal operation and
compatibility with DDR2 SDRAM device and host/
controller offerings, each vendor's AMB will have a
unique set of personality bytes contained in the SPD for
setting up and fine tuning their device.
The FBDIMM specification defines a number of options
to support the requirements of different applications.
The capabilities of the AMB are communicated to the
host during the initialization process in the TS2 training
pattern and in bits readable in the features register in
the AMB.
The AMB is responsible for handling FBDIMM channel
and memory requests to and from the local FBDIMM
and for forwarding requests to other FBDIMMs on
the channel. A complete and detailed description of
the AMB is contained in the proposed FBDIMM AMB
Specification. The AMB is a memory interface that
connects an array of DDR2 SDRAM devices to the
FBDIMM channel. The AMB is a slave device on
the channel responding to channel commands and
forwarding channel commands to other AMB devices.
All memory control for the DDR2 SDRAM resides in the
host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access, and power-
management.
The AMB is expected to perform the following functions:
•
Support channel initialization procedures as
defined in the initialization chapter of the FBDIMM
Architecture and Protocol Specification to align the
clocks and the frame boundaries and verify channel
connectivity
Support the forwarding of southbound and
W3HG128M72AEF-Fx
ADVANCED*
northbound frames, servicing requests directed to a
specific FBDIMM's AMB, as defined in the protocol
chapter of the specification, and merging the return
data into the northbound frames.
•
Initialize northbound frames if the FBDIMM's AMB
is the last, southern-most on the channel, initialize
northbound frames.
Detect errors on the channel and report them to the
host memory controller
Support the FBDIMM configuration register set as
defined in the FBDIMM AMB specification register
chapter of the specification
Act as a DRAM memory buffer for all read, write,
and configuration accesses addressed to a specific
FBDIMM's AMB
Provide a read and write buffer FIFO
Supports an SMBus protocol interface for access to
the AMB configuration registers
Provide features to support MEMBIST and IBIST
test functions
Provide a register interface for the thermal sensor
and status indicator
Function as a repeater to extend the maximum
length of FBDIMM Links
Reconfigures FBDIMM inputs from differential high-
speed link receivers to two single-ended, low-speed
receivers (~200 MHz). These inputs directly control
DDR2 command/address and input data that is
replicated to all DDR2 SDRAMs devices.
Bypass high-speed parallel serial circuitry and
provide test results back to the tester, using low-
speed FBDIMM outputs
•
•
•
•
•
•
•
•
•
•
•
September 2007
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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