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SAA128M4U37YO8ZZF-37E

Description
DRAM
Categorystorage    storage   
File Size11MB,122 Pages
ManufacturerSPECTEK
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SAA128M4U37YO8ZZF-37E Overview

DRAM

SAA128M4U37YO8ZZF-37E Parametric

Parameter NameAttribute value
package instruction,
Reach Compliance Codeunknown
Base Number Matches1
®
512Mb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
SAA128M4..... – 32 Meg x 4 x 4 banks
SAA64M8..... – 16 Meg x 8 x 4 banks
SAA32M16..... – 8 Meg x 16 x 4 banks
For the latest data sheet, please refer to the SpecTek Web site:
http://www.spectek.com
Features
ROHS Compliant
V
DD
= +1.8V ±0.1V,
VDD
Q = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8 configuration
DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL): 3, 4, and 5
Posted CAS additive latency (AL): 0, 1, 2, 3, and 4
WRITE latency = READ latency - 1
t
CK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Options
• SpecTek Memory
• Configuration
128 Meg x 4 (32 Meg x 4 x 4 banks)
64 Meg x 8 (16 Meg x 8 x 4 banks)
32 Meg x 16 (8 Meg x 16 x 4 banks)
• Product Code
DDR2
• Density
512 Megabits
• Voltage/Refresh
1.8V/8K refresh
• FBGA Package – Lead-Free
92-ball FBGA (11mm x 19mm)
84-ball FBGA (12mm x 12.5mm)
60-ball FBGA (12mm x 10mm)
60-ball FBGA (10mm x 10mm)
• FBGA Package – Lead
92-ball FBGA (11mm x 19mm)
84-ball FBGA (12mm x 12.5mm)
60-ball FBGA (12mm x 10mm)
60-ball FBGA (10mm x 10mm)
• Timing – Cycle Time
3.0ns @ CL = 5 (DDR2-667)
3.75ns @ CL = 4 (DDR2-533)
Notes: 1.
2.
Designation
SAA
128M4
64M8
32M16
Ux
1
7x
1
O8
ZZF
FYF
FMF
FSF
ZZL
FYL
FML
FSL
-3
-37E
Table 1:
Architecture
Configuration Addressing
128 Meg x 4 64 Meg x 8 32 Meg x 16
16 Meg x 8 x
4 banks
8K
16K (A0–A13)
4 (BA0–BA1)
1K (A0–A9)
8 Meg x 16 x
4 banks
8K
8K (A0–A12)
4 (BA0–BA1)
1K (A0–A9)
Configuration 32 Meg x 4 x 4
banks
8K
Refresh Count
16K (A0–A13)
Row Addr.
4 (BA0–BA1)
Bank Addr.
Column Addr. 2K (A0–A9, A11)
Table 2:
Speed
Grade
-37E
-3
Key Timing Parameters
Data Rate (MHz)
CL = 3 CL = 4 CL = 5
400
NA
533
533
NA
667
t
RCD
t
RP
t
RC
(ns)
15
15
(ns)
15
15
(ns)
55
55
Part Number Example:
SAA64M8U37YO8FSF-3
Contact SpecTek Sales for details on availability of the
“x” placeholders.
See page 121 for part number options and designations
used prior to July 2006.
PDF: 09005aef81adff0b/Source: 09005aef81adfede
SpecTek_DDR2_512Mb_1.fm - Rev. C 12/06 EN
1
SpecTek reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.

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Description DRAM DRAM DRAM DRAM
Reach Compliance Code unknown unknown unknown unknown
Base Number Matches 1 1 1 1

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