M27V402
4 Mbit (256Kb x16) Low Voltage UV EPROM and OTP EPROM
NOT FOR NEW DESIGN
s
s
M27V402 is replaced by the M27W402
LOW VOLTAGE READ OPERATION:
3V to 3.6V
ACCESS TIME: 120ns
LOW POWER CONSUMPTION:
– Active Current 15mA at 5MHz
– Standby Current 20µA
1
1
40
40
s
s
s
s
s
PROGRAMMING VOLTAGE: 12.75V
±
0.25V
PROGRAMMING TIME: 100µs/word
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 8Dh
FDIP40W (F)
PDIP40 (B)
DESCRIPTION
The M27V402 is a low voltage, low power 4 Mbit
UV erasable and electrically programmable
EPROM, ideally suited for handheld and portable
microprocessor systems requiring large programs.
It is organized as 262,144 by 16 bits.
The M27V402 operates in the read mode with a
supply voltage as low as 3V. The decrease in op-
erating power allows either a reduction of the size
of the battery or an increase in the time between
battery recharges.
The FDIP40W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V256 is offered in PDIP40, PLCC44 and
TSOP40 (10 x 20 mm) packages.
PLCC44 (K)
TSOP40 (N)
10 x 20 mm
Figure 1. Logic Diagram
VCC
VPP
18
A0-A17
16
Q0-Q15
E
G
M27V402
VSS
AI01819
July 2000
This is information on a product still in production but not recommended for new designs.
1/15
M27V402
Figure 2A. DIP Connections
VPP
E
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
VSS
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
G
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
M27V402
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
AI01862
Figure 2B. LCC Connections
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
Q12
Q11
Q10
Q9
Q8
VSS
NC
Q7
Q6
Q5
Q4
Q13
Q14
Q15
E
VPP
NC
VCC
A17
A16
A15
A14
1 44
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
12
M27V402
34
23
Q3
Q2
Q1
Q0
G
NC
A0
A1
A2
A3
A4
AI01820
Figure 2C. TSOP Connections
A9
A10
A11
A12
A13
A14
A15
A16
A17
VCC
VPP
E
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
1
40
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
G
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
Table 1. Signal Names
A0-A17
Q0-Q15
E
G
V
PP
V
CC
V
SS
NC
Address Inputs
Data Outputs
Chip Enable
Output Enable
Program Supply
Supply Voltage
Ground
Not Connected Internally
10
11
M27V402
(Normal)
31
30
20
21
AI01821
2/15
M27V402
Table 2. Absolute Maximum Ratings
(1)
Symbol
T
A
T
BIAS
T
STG
V
IO (2)
V
CC
V
A9 (2)
V
PP
Parameter
Ambient Operating Temperature
(3)
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
A9 Voltage
Program Supply Voltage
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
–2 to 7
–2 to 13.5
–2 to 14
Unit
°C
°C
°C
V
V
V
V
Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
CC
+0.5V with possible overshoot to V
CC
+2V for a period less than 20ns.
3. Depends on range.
Table 3. Operating Modes
Mode
Read
Output Disable
Program
Verify
Program Inhibit
Standby
Electronic Signature
Note: X = V
IH
or V
IL
, V
ID
= 12V
±
0.5V.
E
V
IL
V
IL
V
IL
Pulse
V
IH
V
IH
V
IH
V
IL
G
V
IL
V
IH
V
IH
V
IL
V
IH
X
V
IL
A9
X
X
X
X
X
X
V
ID
V
PP
V
CC
or V
SS
V
CC
or V
SS
V
PP
V
PP
V
PP
V
CC
or V
SS
V
CC
Q15-Q0
Data Out
Hi-Z
Data In
Data Out
Hi-Z
Hi-Z
Codes
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
V
IL
V
IH
Q7
0
1
Q6
0
0
Q5
1
0
Q4
0
0
Q3
0
1
Q2
0
1
Q1
0
0
Q0
0
1
Hex Data
20h
8Dh
Note: Outputs Q15-Q8 are set to ’0’.
3/15
M27V402
Table 5. AC Measurement Conditions
High Speed
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
10ns
0 to 3V
1.5V
Standard
≤
20ns
0.4V to 2.4V
0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
3V
1.5V
0V
DEVICE
UNDER
TEST
2.0V
0.8V
AI01822
1N914
3.3kΩ
Standard
2.4V
OUT
CL
0.4V
CL = 30pF for High Speed
CL = 100pF for Standard
CL includes JIG capacitance
AI01823B
Table 6. Capacitance
(1)
(T
A
= 25
°C,
f = 1 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Condit ion
V
IN
= 0V
V
OUT
= 0V
Min
Max
6
12
Unit
pF
pF
Note: 1. Sampled only, not 100% tested.
DEVICE OPERATION
The operating modes of the M27V402 are listed in
the Operating Modes table. A single power supply
is required in the read mode. All inputs are TTL
levels except for V
PP
and 12V on A9 for Electronic
Signature.
Read Mode
The M27V402 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins,
independent of device selection. Assuming that
the addresses are stable, the address access time
(t
AVQV
) is equal to the delay from E to output
(t
ELQV
). Data is available at the output after a delay
of t
GLQV
from the falling edge of G, assuming that
E has been low and the addresses have been
stable for at least t
AVQV
-t
GLQV
.
Standby Mode
The M27V402 has a standby mode which reduces
the supply current from 20mA to 20µA with low
voltage operation V
CC
≤
3.6V, see Read Mode DC
Characteristics table for details. The M27V402 is
placed in the standby mode by applying a CMOS
high signal to the E input. When in the standby
mode, the outputs are in a high impedance state,
independent of the G input.
4/15
M27V402
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70°C, –20 to 70°C, –20 to 85°C or –40 to 85°C; V
CC
= 3.3V
±
10%; V
PP
= V
CC
)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
I
PP
V
IL
V
IH (2)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
Output High Voltage CMOS
I
OL
= 2.1mA
I
OH
= –400µA
I
OH
= –100µA
2.4
V
CC
–0.7V
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IL
, I
OUT
= 0mA,
f = 5MHz, V
CC
= 3.6V
E = V
IH
E > V
CC
– 0.2V, V
CC
= 3.6V
V
PP
= V
CC
–0.3
2
Min
Max
±10
±10
20
1
20
10
0.8
V
CC
+ 1
0.4
Unit
µA
µA
mA
mA
µA
µA
V
V
V
V
V
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, the product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, I
CC
, has three seg-
ments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
output capacitive and inductive loading of the de-
vice.
The associated transient voltage peaks can be
suppressed by complying with the two line output
control and by properly selected decoupling ca-
pacitors. It is recommended that a 0.1µF ceramic
capacitor be used on every device between V
CC
and V
SS
. This should be a high frequency capaci-
tor of low inherent inductance and should be
placed as close to the device as possible. In addi-
tion, a 4.7µF bulk electrolytic capacitor should be
used between V
CC
and V
SS
for every eight devic-
es. The bulk capacitor should be located near the
power supply connection point.The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.
5/15
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