PEB2256 datasheet, PDF - EEWORLD Datasheet

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PEB2256: DescriptionFramer, CMOS, PQFP80,; CategoryWireless rf/communication Telecom circuit; File Size93KB，2 Pages; ManufacturerSIEMENS; Websitehttp://www.infineon.com/

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PEB2256 Overview

Framer, CMOS, PQFP80,

PEB2256 Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknown
JESD-30 code	S-PQFP-G80
Number of functions	1
Number of terminals	80
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Telecom integrated circuit types	FRAMER
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal location	QUAD
Base Number Matches	1

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Product Brief

FALC 56

PEB 2256

E1/T1/J1

Frame

Line

Interface

Component

for Long and Short

Haul Applications

The FALC56 (PEB 2256) is the

latest member of the FALC family

and has been optimized to realize

generic long-haul and short-haul

solutions for 3.3 V network equip-

ment. All standard E1/T1/J1

Applications

Wireless Basestations

T1/E1/J1 ATM Gateways

T1/E1/J1 Frame Relay

Gateways

T1/E1/J1 Channel & Data

Service Units (CSU,DSU)

ISDN PRI, PBXs

T1/E1/J1 Internet Access Equip.

LAN/WAN Router

SONET/SDH Add/Drop MUXs

T1/E1/J1 Multiplexer

Digital Access Cross-Connect

Systems (DACS)

Features

Analog Line Interface

Analog receive & transmit

circuitry long haul & short haul

for E1/T1/J1 applications

Clock & data recovery

Crystal-less wander and jitter

attenuation/compensation acc.

TR 62411, ETS-TBR 12/13

Clock generation unit accepts

flexible frequency reference

clocks

Transmit line monitoring

Programmable transmit pulse

shape for flexible pulse genera-

tion

Support of automatic protection

switching

formats are supported and can be

easily selected via software.

Comprising features like Signal

System #7 support, crystal-less

wander & jitter attenuation, flexible

frequency reference clock and

Frame Aligner

ITU-T G. 704 Frame alignment/

synthesis for 2048/1544 kbit/s

Programmable frame formats:

E1: Double-& CRC Multiframe

T1: F4, F12 (D4), Ext. Super

Frame (ESF), F72 (SLC96)

CRC-4/6 performance monitoring

Alarm & performance

monitoring per second

Detects & generates LOS (red),

AIS (blue) & RAI (yellow) alarms

System bus data rate scalable

from 1.544 MHz up to 16 MHz

Signaling Controller

HDLC/LAPD controller (Q.921)

with deep FIFO buffers (64 bytes)

CAS controller with serial CAS

in/output to system interface

Supports signaling system #7

ANSI T1.403 Bit-Oriented Mes-

sages (BOM), generates period-

ical performance reports

Time-Slot 0 SA

8- 4

bit handling in

via FIFOs

General Features

8/16 bit

µP

interface INTEL or

MOTOROLA type

Meets japanese requirements

as: JT G. 703, 704, 706, I.431

FALC56

Test functions e.g. PRBS,

system data rates up to 16 Mbit/s

the FALC56 is excellent suited for

building state-of-the-art Wireless

Basestations, Switches and

Internet Access Equipment.

Local-, Remote- & Payload Loop

Based on PEB 22554

QuadFALC

design

32 maskable interrupt sources

Internal/external second timer

Real software switchable

E1/T1/J1 device

Single 3.3 V power supply

JTAG Boundary scan

IEEE1149.1

3.3 V CMOS technology,

5 V tolerant inputs

P- MQFP- 80 package;

body size 14x14; pitch 0.65

Power consumption is 220 mW

typically

Documentation and Support

Package

Data Sheet

Application Notes

Transformer recommendations

CD-ROM Support Package

Hardware Evaluation System

EASY 2256 with Software for

MS Windows 95/NT

Support Software (low level

driver, LAPD Protocol S/W)

http://www.siemens.de/semiconductor/falc

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