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CY28326OC

Description
FTG for VIA PT880 Serial Chipset
File Size226KB,22 Pages
ManufacturerSpectraLinear
Websitehttp://www.spectralinear.com/
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CY28326OC Overview

FTG for VIA PT880 Serial Chipset

CY28326
FTG for VIA PT880 Serial Chipset
Features
• Supports P4 CPUs
• 3.3V power supply
• Ten copies of PCI clocks
• One 48 MHz USB clock
• Two copies of 25 MHz for SRC/LAN clocks
• One 48 MHz/24 MHz programmable SIO clock
• Three differential CPU clock pairs
• SMBus support with Byte Write/Block Read/Write
capabilities
• Spread Spectrum EMI reduction
• Dial-A-Frequency
®
features
• Auto Ratio features
• 48-pin SSOP package
Block Diagram
Pin Configuration
[1]
XIN
XOUT
REF[0:2]
PLL1
CPU_STP#
IREF
Power
on
Latch
/2
CPUT[0:2]
CPUC[0:2]
25MHz[0:1]
AGP[0:2]
FS[A:D]
VTTPWRGD#
PCI_STP#
**FSA/REF0
**FSB/REF1
VDDREF
XIN
XOUT
VSSREF
*FSC/PCIF0
*FSD/PCIF1
*Mode/PCIF2
VDDPCI
VSSPCI
PCI0
PCI1
PCI2
PCI3
PCI4
VDDPCI
VSSPCI
*(PCI_STP#)/Ratio0/PCI5
*(CPU_STP#)/Ratio1/PCI6
48MHz
**24_48_SEL/24_48MHz
VSS48
VDD48
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
VDDA
VSSA
IREF
CPUT2
CPUC2
VSSCPU
CPUT1
CPUC1
VDDCPU
CPUT0
CPUC0
VSSSRC
25MHz1
25MHz0
VDDSRC
*VTT_PWRGD/*PD#
SD
ATA
SCLK
SRESET#
AGP2
VSSAGP
VDDAGP
AGP1/*RatioSel
AGP0
CY2 8 3 2 6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCI[0:6]
PCI_F[0:2]
PLL2
MODE
48MHz
24_48MHz
PD#
SDATA
SCLK
WD
Logic
I2C
Logic
SRESET
48 Pin SSOP
Note:
1. Pins marked with [*] have internal 150k
pull-up resistors. Pins marked with [**] have internal 150k
pull-down resistors.
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 22
www.SpectraLinear.com

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