PRELIMINARY
CY28412
Clock Generator for Intel
®
Grantsdale Chipset
Features
• Supports Intel P4 and Prescott CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100 MHz differential SRC clocks
• 96 MHz differential dot clock
• 48 MHz USB clocks
• 33 MHz PCI clock
CPU
x2 / x3
SRC
x7 / x8
PCI
x8
REF
x2
DOT96
x1
USB_48
x1
• Low-voltage frequency select input
• I
2
C Support with read back capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP package
Block Diagram
XIN
XOUT
CPU_STP#
PCI_STP#
FS_[C:A]
VTT_PWRGD#
IREF
Pin Configuration
PCI0
PCI1
VDD_PCI
VDD_CPU
GND_PCI
CPUT[0:1], CPUC[0:1],
CPU(T/C)2_ITP]
PCI2
VDD_SRC
PCI3
SRCT[0:6], SRCC[0:6],
PCI4
SATA[T/C]
PCI5
GND_PCI
VDD_PCI
VDD_PCI
TEST_SEL/PCIF0
PCI[0:5]
ITP_EN/PCIF1
VDD_PCIF
PCIF[0:1]
VDD_48
USB48/FS_B
GND_48
VDD_48 MHz
DOT96T
DOT96T
DOT96C
DOT96C
VTT_PwrGd#/PD
USB_48
SRCT0
SRCC0
SRCT1
STCC1
VDD_SRC
GND_SRC
SRCT2
SRCC2
SATAT
SATAC
VDD_REF
REF[1:0]
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
PD
PLL2
SDATA
SCLK
I
2
C
Logic
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
REF0/FS_C
REF1/FS_A
GND_REF
X1
X2
SDATA
SCLK
GND_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
GND_A
VDD_A
CPUT2_ITP/SRCT6
CPUC2_ITP/SRCC6
VDD_SRC
SRCT5
SRCC5
GND_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VDD_SRC
56 SSOP
CY28412
Rev 1.0, November 20, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 16
www.SpectraLinear.com
CY28412
Pin Definitions
Pin No.
47,46,44,43
39,38
CPUT/C
CPUT2_ITP/SRCT6,
CPUC2_ITP/SRCC6
DOT96T, DOT96C
REF0/FS_C,
REF1/FS_A
USB48/FS_B
Name
Type
O, DIF
Differential CPU clock outputs.
O, DIF
Selectable Differential CPU or SRC clock output.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC6
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
O, DIF
Fixed 96-MHz clock output.
I/O
14.318-MHz reference clock/3.3V-tolerant input for CPU frequency selection.
Input is latched upon assertion (LOW) of VTT_PWRGD#/PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Fixed 48-MHz USB clock output/3.3V-tolerant input for CPU frequency
selection.
Input is latched upon assertion (LOW) of VTT_PWRGD#/PD
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
A precision resistor is attached to this pin, which is connected to the
internal current reference.
Free-running 33-MHz clocks/ 3.3V-tolerant input for selecting test mode.
Input is latched upon assertion (LOW) of VTT_PWRGD#/PD
1 = All outputs are three-stated for test
0 = All outputs normal operation
**This input has an internal pull-down resistor.
Description
16,17
55, 54
14
I/O
42
1,2,5,6,7,8
11
IREF
PCI[0:5]
TEST_SEL/PCIF0
I
O, SE
33-MHz clocks.
I/O
12
ITP_EN/PCIF1
I/O, SE
Free-running 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD#
assertion).
1 = CPU2_ITP, 0 = SRC6
I
I/O
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
49
50
27,28
SCLK
SDATA
SATAT, SATAC
O, DIF
Differential serial reference clock.
Recommended output for SATA.
O, DIF
Differential serial reference clocks.
19,20,21,22, SRCT/C[0:5]
25,26,30,31,
32,33,35,36
13
45
3,10
56
23,29,37
40
15
48
4,9
53
24,34
41
18
VDD_48
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDD_A
GND_48
GND_CPU
GND_PCI
GND_REF
GND_SRC
GND_A
VTT_PWRGD#/PD
PWR
PWR
PWR
PWR
PWR
PWR
GND
GND
GND
GND
GND
GND
I, PU
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for outputs.
3.3V power supply for PLL.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for PLL.
3.3V LVTTL input is a level sensitive strobe used to latch the REF0/FSC,
REF1/FSA, USB48/FSB, TEST_SEL/PCIF0 and ITP_EN/PCIF1 inputs.
After
VTT_PWRGD# (active LOW) assertion, this pin becomes a realtime input for
asserting power-down (active HIGH).
14.318-MHz crystal input.
52
51
X1
X2
I
O, SE
14.318-MHz crystal output.
Rev 1.0, November 20, 2006
Page 2 of 16
CY28412
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
izes to their default setting upon power-up, and therefore use
of this interface is optional. Clock device register changes are
normally made upon system initialization, if any are required.
The interface cannot be used during system operation for pow-
er management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in se-
quential order from lowest to highest byte (most significant bit
first) with the ability to stop after any complete byte has been
transferred. For byte write and byte read operations, the sys-
tem controller can access individually indexed bytes. The off-
set of the indexed byte is encoded in the command code, as
described in
Table 2.
The block write and block read protocol is outlined in
Table 3
while
Table 4
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface initial-
Table 1. Frequency Select Table (FS_A, FS_B, FS_C)
FS_C
1
0
0
0
0
1
1
1
FS_B
0
0
1
1
0
0
1
1
FS_A
1
1
1
0
0
0
0
1
CPU
100 MHz
133 MHz
166 MHz
200 MHz
266 MHz
333 MHz
400 MHz
Reserved
SRC
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
REF0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
DOT96
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
96 MHz
USB
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
48 MHz
Table 2. Command Code Definition
Bit
7
Description
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'00000000' stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge from master
Block Read Protocol
Description
Rev 1.0, November 20, 2006
Page 3 of 16
CY28412
Table 3. Block Read and Block Write Protocol
(continued)
Block Write Protocol
Bit
....
....
....
....
....
....
......................
Data Byte (N – 1) – 8 bits
Acknowledge from slave
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
39:46
47
48:55
56
....
....
....
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of the
command code represents the offset of the byte to
be accessed
Acknowledge from slave
Data byte from master – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write = 0
Acknowledge from slave
Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[6:0] of
the command code represents the offset of the
byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read = 1
Acknowledge from slave
Data byte from slave – 8 bits
Acknowledge from master
Stop
Byte Read Protocol
Description
Block Read Protocol
Description
Data byte from slave – 8 bits
Acknowledge from master
Data byte from slave – 8 bits
Acknowledge from master
Data byte N from slave – 8 bits
Acknowledge from master
Stop
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Control Registers
Byte 0:Control Register 0
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
CPUT2_ITP/SRCT6
CPUC2_ITP/SRCC6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SATAT/C]
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
Description
CPU[T/C]2_ITP/SRC[T/C]6 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SATA[T/C] Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enable
SRC[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enable
Rev 1.0, November 20, 2006
Page 4 of 16
CY28412
Byte 1: Control Register 1
Bit
7
@Pup
1
Name
CPUT/C
SRCT/C
PCIF
PCI
DOT_96T/C
USB_48
REF0
REF1
CPU[T/C]1
CPU[T/C]0
CPUT/C
SRCT/C
PCIF
PCI
Description
Center Spread Enable
0 = ±0.25% Center Spread, 1 = –0.5% Down Spread
6
5
4
3
2
1
0
1
1
1
1
1
1
0
DOT_96 MHz Output Enable
0 = Disable (Hi-Z), 1 = Enabled
USB_48 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
CPU[T/C]1 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
CPU[T/C]0 Output Enable
0 = Disable (Hi-Z), 1 = Enabled
Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Byte 2: Control Register 2
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Name
PCI5
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF1
PCIF0
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Description
Byte 3: Control Register 3
Bit
7
6
5
4
3
@Pup
0
0
0
0
0
Name
CPUT2_ITP/SRCT6
CPUC2_ITP/SRCC6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SATA[T/C]
Description
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]5with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]3with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SATA[T/C] with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Rev 1.0, November 20, 2006
Page 5 of 16
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