W312-02
FTG for VIA™ K7 Series Chipset
with Programmable Output Frequency
Features
• Single chip FTG solution for VIA™ K7 Series chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when watchdog timer
time-out
• Capable of generate system RESET after a watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength for PCI output clocks
• Programmable output skew between CPU, AGP and PCI
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Low jitter and tightly controlled clock skew
• Two pairs of differential CPU clocks
• Eleven copies of PCI clocks
• Three copies of 66-MHz outputs
• Two copies of 48-MHz outputs
• Three copies of 14.31818-MHz reference clocks
• One RESET output for system recovery
• Power management control support
Key Specifications
CPU Outputs Cycle-to-cycle Jitter: ............................. 250 ps
48-MHz, 3V66, PCI Outputs
Cycle-to-cycle Jitter: .................................................... 500 ps
CPU, 3V66 Output Skew:............................................ 200 ps
48-MHz Output Skew: ................................................. 250 ps
PCI Output Skew:........................................................ 500 ps
Block Diagram
VDD_REF
Pin Configuration
REF2
REF1/FS1*
REF0/FS0*
[1]
X1
X2
XTAL
OSC
PLL REF FREQ
VDD_CPU
Divider,
Delay,
and
Phase
Control
Logic
CPUT0,CPUC0
2
SDATA
SCLK
SMBus
Logic
CPUT_CS,CPUC_CS
VDD_AGP
3
AGP0:2
(FS0:4)
VDD_PCI
PCI0/SEL24_48#*
PLL 1
PD#
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
5
PCI1:8
PCI9_E
RST#
VDD_48MHz
48MHz/FS3*
VDD_REF
GND_REF
X1
X2
VDD_48MHz
*FS2/48MHz
*FS3/24_48MHz
GND_48MHz
*FS4/PCI_F
*SEL24_48#/PCI0
PCI1
GND_PCI
PCI2
PCI3
VDD_PCI
PCI4
PCI5
PCI6
GND_PCI
PCI7
PCI8
PCI9_E
VDD_PCI
RST#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/FS0*
REF1/FS1*
REF2
REF_STOP#*
AGP_STOP#*
GND_CPU
CPUT0
CPUC0
VDD_CPU
CPUT_CS
CPUC_CS
GND_CPU
CPU_STOP#*
PCI_STOP#*
PD#*
VDD_CORE
GND_CORE
SDATA
SCLK
GND_AGP
AGP2
AGP1
AGP0
VDD_AGP
PLL2
/2
SEL24_48#*
24_48MHz/FS4*
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. De-
sign should not rely solely on internal pull-up resistor to set I/O pins
HIGH.
W312-02
Rev 1.0, November 27, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 19
www.SpectraLinear.com
W312-02
I
Pin Definitions
Pin Name
REF0/FS0
Pin No.
48
Pin
Type
I/O
Pin Description
Reference Clock Output 0/Frequency Select 0:
3.3V 14.318-MHz clock
output. REF0 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 5.
Reference Clock Output 0/Frequency Select 1:
3.3V 14.318-MHz clock
output. REF1 will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determines device operating frequency as described in
Table 5.
Reference Clock Output 2:
3.3V 14.318-MHz clock output. REF2 will be
disabled when REF_STOP# is active.
Crystal Input:
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output:
An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
Free-Running PCI Clock/Frequency Select 4:
3.3V 33-MHz free running PCI
clock output. This pin also serves as the select strap to determines device
operating frequency as described in
Table 5.
PCI Clock 0/Select 24 or 48 MHz:
3.3V 33-MHz PCI clock outputs. This output
will be disabled when PCI_STOP# is active. This pin also serves as the select
strap to determine device operating frequency of 24_48MHz output.
PCI Clock 1 through 8:
3.3V 33-MHz PCI clock outputs. PCI1:8 will be disabled
when PCI_STOP# is active.
Early PCI Clock 9:
3.3V 33-MHz PCI clock outputs. PCI9_E will be disabled
when PCI_STOP# is active.
AGP Clock 0 through 2:
3.3V 66-MHz clock outputs. The operating frequency
is controlled by FS0:4 (see
Table 5).
AGP0:2 will be disabled when
AGP_STOP# is active.
48-MHz Output/Frequency Selection 3:
3.3V 48-MHz non-spread spectrum
output. 48MHz will be disabled when REF_STOP# is active. This pin also serves
as the select strap to determine device operating frequency as described in
Table 5.
24 or 48-MHz Output/Select 24 or 48 MHz:
3.3V 24 or 48-MHz non-spread
spectrum output. 24_48MHz will be disabled when REF_STOP# is active. This
pin also serves as the select strap to determine device operating frequency as
described in
Table 5.
REF1/FS1
47
I/O
REF2
X1
X2
PCI_F/FS4
46
3
4
9
I/O
I
I
I
PCI_0/SEL24_48#
10
I/O
PCI1:8
PCI9_E
AGP0:2
11, 13, 14, 16,
17, 18, 20, 21
22
26, 27, 28
O
O
O
48MHz/FS2
6
I/O
24_48MHz/FS3
7
I/O
RST#
24
Reset#:
Open-drain RESET# output.
O
(open-d
rain)
O
CPU Clock Output 0:
CPUT0 and CPUC0 are the differential CPU clock
(open-d outputs for the K7 processor. They are open-drain outputs.
rain)
O
CPU Clock Output for Chipset:
CPUT_CS and CPUC_CS are the differential
CPU clock outputs for the chipset. They are push-pull outputs. These outputs
will be disabled when CPU_STOP# is active.
CPU STOP Input:
This input will disable CPUT_CS and CPUC_CS when it is
active.
PCI STOP Input:
This input will disable PCI0:8 and PCI9_E when it is active.
AGP STOP Input:
This input will disable AGP0:2 when it is active.
REF STOP Input:
This input will disable REF0:2, 24_48MHz and 48 MHz
outputs when it is active.
CPUT0, CPUC0
42, 41
CPUT_CS,
CPUC_CS
CPU_STOP#
PCI_STOP#
AGP_STOP#
REF_STOP#
39, 38
36
35
44
45
I
I
I
I
Rev 1.0, November 27, 2006
Page 2 of 19
W312-02
Pin Definitions
(continued)
Pin Name
PD#
SDATA
SCLK
VDD_CPU
VDDQ_AGP
VDDQ_PCI
VDDQ_48MHz
VDD_REF
VDD_Core
GND_REF,
GND_48MHz,
GND_PCI,
GND_AGP,
GND_Core,
GND_CPU
Pin No.
34
31
30
40
25
15, 23
5
1
33
2, 8, 29, 32, 37,
43
Pin
Type
I
I/O
I
P
P
P
P
P
P
G
Pin Description
Power-Down Input:
This input will trigger the clock generator into Power Down
mode when it is active.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
2.5V Power Connection:
Power supply for CPU output buffers. Connect to
2.5V.
3.3V Power Connection:
Power supply for AGP output buffers. Connect to
3.3V.
3.3V Power Connection:
Power supply for PCI output buffers. Connect to 3.3V.
3.3V Power Connection:
Power supply for 48 MHz output buffers. Connect to
3.3V.
3.3V Power Connection:
Power supply for reference output buffers. Connect
to 3.3V.
3.3V Power Connection:
Power supply for PLL core. Connect to 3.3V.
Ground Connections:
Connect all ground pins to the common system ground
plane.
Rev 1.0, November 27, 2006
Page 3 of 19
W312-02
Serial Data Interface
The W312-02 features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word write,
byte/word read, block write and block read operations from the
controller. For block write/read operation, the bytes must be
Table 1. Command Code Definitions
Bit
7
6:0
Descriptions
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been trans-
ferred. For byte/word write and byte read operations, system
controller can access individual indexed byte. The offset of the
indexed byte is encoded in the command code.
.The
block write and block read protocol is outlined in
Table 1
while
Table 2
outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h)
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
1
2:8
9
10
11:18
19
20:27
28
29:36
37
38:45
46
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
19
20
21:27
28
29
30:37
38
39:46
47
48:55
56
...
...
...
...
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
Rev 1.0, November 27, 2006
Page 4 of 19
W312-02
Table 3. Word Read and Word Write Protocol
Word Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits (D2)
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte low – 8 bits
Acknowledge from slave
Data byte high – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits (D3)
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte low from slave – 8 bits
Acknowledge
Data byte high from slave – 8 bits
NOT acknowledge
Stop
Word Read Protocol
Description
19
20:27
28
29:36
37
38
19
20
21:27
28
29
30:37
38
39:46
47
48
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Description
Bit
1
2:8
9
10
11:18
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘1xxxxxxx’ stands for byte operation
bit[6:0] of the command code represents the
offset of the byte to be accessed
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Data byte from slave – 8 bits
Not Acknowledge
Stop
Byte Read Protocol
Description
19
20:27
28
29
19
20
21:27
28
29
30:37
38
39
Rev 1.0, November 27, 2006
Page 5 of 19
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