64MX 64 UNBUFFERED SDRAM SODIMM
SDRAM SODIMM MODULE
512 MByte (64M x 64) SDRAM
Unbuffered 144 Pin SODIMM
LOW PROFILE (1.03 inch height)
General Description:
This memory module is a high performance 512 Megabyte Unbuffered synchronous dynamic
RAM module organized as 64M x 64 in a 144 pin Small Outline Dual In-Line Memory Module
(SODIMM) package. The module utilizes eight (8) 8Mx4X16 512MbitSDRAM
1
devices in a
TSOP II 400 mil package. A 256 Byte Serial EEPROM contains the module configuration
information. The EEPROM can be configured to a customer’s specifications.
These modules offer substantial advances in SDRAM operating performance, including the
ability to synchronously burst data at a high rate with automatic column-address generation,
interleave between internal banks in order to hide precharge time, and the capability to
randomly change column address on each clock cycle during burst.
Features:
♦
High density:
♦
Cycle time:
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
512 MB (64M x 64)
10 ns (100 MHz)
7.5 ns (133 MHz)
JEDEC Standard 144 Pin Unbuffered SDRAM SODIMM Pinout
PC133 and PC100 Compliant
Single power supply of 3.3V ± 10%
Serial Presence Detect
LVTTL Compatible I/O and Clock
Unbuffered Control and Address Lines
Auto Precharge handled by SDRAM Devices
Refresh 8K rows every 64ms
Programmable Burst Type, Burst Length and CAS Latency of SDRAM Devices
Internal Pipeline Operation
Fully Synchronous – all signals registered on positive edge of system clock
Package Height: 1.03 inches (+/- 10mils)
1
Based on ELPIDA 512Mbit HM5257165B-75A
Kentron Technologies, Inc.
155 West Street
♦
Wilmington, MA 01887
Phone: (978) 988-9100
♦
Fax (978) 988-5550
www.kentrontech.com
64M X 64 UNBUFFERED SDRAM SODIMM
Operating Features:
The SDRAM SODIMM utilizes a clock input for the synchronization. Each operation of the
SDRAM is determined by commands and all operations are referenced to a positive clock edge.
CAS Latency defines the delay from when a Read Command is registered on a rising clock
edge to when the data from the Read Command becomes available at the outputs. The CAS
latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock
cycles.
The burst mode is a very high-speed access mode utilizing an internal column address
generator. Once a column address for the first access is set, following addresses are
automatically generated by the internal column address counter.
All control and address signals are supplied from the chipset through an unbuffered path to the
SDRAMs. There are two clock signals supplied by the motherboard to synchronize the
SODIMM.
Kentron Technologies, Inc. (978) 988-9100
Rev. 4/02
Page 2
64M X 64 UNBUFFERED SDRAM SODIMM
Absolute Maximum Ratings*:
Item
Supply voltage (V
CC
Relative to V
SS
)
Input/Output Voltage
Operating temperature
Storage temperature
Short circuit output current
Symbol
V
CC
V
I/O
T
opr
T
stg
I
out
Rating
-1.0 to +4.6
-1.0 to +4.6
0 to +70
-55 to +125
±50
Unit
V
V
°C
°C
MA
* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions:
(Voltage referenced to V
CC
. T
A
= 0 to 70 °C)
Item
Supply voltage
Input high voltage
Input low voltage
Operating Temperature
Symbol
V
DD
V
IH
V
IL
T
A
Min.
3.1
2.0
-0.3
0
Typ.
3.3
-
-
+25
Max.
3.5
V
DD
+0.3
0.8
+70
Unit
V
V
V
°C
Capacitance:
(TA=25°C, Vcc=3.3V±0.3V)
Parameter
Input capacitance (Address, /WE, CKE0,1 , /CAS)
Input capacitance ( /CS0~/CS1)
Input capacitance (/DQMBs)
Input capacitance (CK0, CK1)
Input capacitance (/RAS)
Input/Output capacitance (DQ0~DQ63, CB0~CB7)
Symbol
C
IN
C
IN
C
IN
C
IN
C
IN
C
I/O
Max.
45
28
14
28
56
16
Unit
pF
pF
pF
pF
pF
pF
Kentron Technologies, Inc. (978) 988-9100
Rev. 4/02
Page 3
64M X 64 UNBUFFERED SDRAM SODIMM
Pin Names:
CK0-CK3
CKE0
/RAS
/CAS
/WE
/CS0-/CS3
A0-A11
BA0, BA1
NC or DU
Clock Inputs
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Select
Address Inputs
SDRAM Bank Select
No Connect
DQ0-DQ63
CB0-CB7
/DQMB0-/DQMB7
V
DD
V
SS
SCL
SDA
SA0-SA2
WP
Data Inputs/Outputs
ECC Data Input/Output
Data Mask Enables
Power supply
Ground
Serial Clock
Serial Data Input/Output
Decode Input
Write Protect for SPD
SDRAM Pinout:
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Designation
Vss
Vss
DQ0
DQ32
DQ1
DQ33
DQ2
DQ34
DQ3
DQ35
No.
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Designation
DQ8
DQ40
DQ9
DQ41
DQ10
DQ42
DQ11
DQ43
No.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Designation
NU
CK1
Vss
Vss
NC
NC
NC
NC
No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Designation
A9
BA1
A10/AP
A11
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
DQ4
DQ36
DQ5
DQ37
DQ6
DQ38
DQ7
DQ39
Vss
Vss
DQMB0
DQMB4
DQMB1
DQMB5
V
DD
V
DD
A0
A3
A1
A4
A2
A5
Vss
Vss
DQ12
DQ44
DQ13
DQ45
DQ14
DQ46
DQ15
DQ47
Vss
Vss
NC
NC
NC
NC
CK0
CKE0
V
DD
V
DD
DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51
Vss
Vss
DQ20
DQ52
DQ21
DQ53
DQ22
DQ54
DQ23
DQ55
DQMB2
DQMB6
DQMB3
DQMB7
Vss
Vss
DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59
V
DD
V
DD
RAS
CAS
WE
CKE1
S0
A12
S1
A13
V
DD
V
DD
A6
A7
A8
BA0
Vss
Vss
DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63
Vss
Vss
SDA
SCL
V
DD
V
DD
Kentron Technologies, Inc. (978) 988-9100
Rev. 4/02
Page 4
64M X 64 UNBUFFERED SDRAM SODIMM
DC Characteristics:
(
V
DD
= 3.3V±.3V, V
SS
=0V, T
A
=0 to + 70°C)
Parameter
2
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
133MHz
Max.
880
48
320
32
240
760
1320
48
100MHz
Max.
880
48
320
32
240
760
1320
48
Unit
mA
mA
Operating current
(No Burst, T
CK
=min. T
RC
=min. Single Bank)
Precharge Standby Current
(CKE=V
IL
, T
CK
= min. All banks idle)
(CKE=V
IH
, T
CK
= min. All banks idle)
Active Standby Current
(CKE=V
IL
, T
CK
= min. One bank active)
(CKE=V
IH
, T
CK
= min. One bank active)
Burst Mode Current (t
CK
=min.)
Refresh Current (per DIMM bank)
(t
CK
=min., t
RC
=min., t
RRD
=min., Auto Refresh)
Self Refresh Current (all DIMM banks, CKE=V
IL
)
mA
mA
mA
mA
AC Electrical Characteristics:
(TA=0°C to +70°C,
V
DD
=3.3V±0.3V,
V
DD
=0V)
Parameter
Row to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new Col. Address delay
Last data in to burst stop
Column address to column address delay
Number of valid output data
(CL=3)
(CL=2)
Clock Cycle Time
(CL=3)
(CL=2)
Clock to Valid Output Delay
(CL=3)
(CL=2)
Output Data Hold Time
(CL=3)
(CL=2)
Clock High Pulse Width
Clock Low Pulse Width
Input Setup Time
Input Hold Time
Clock to Output in Low-Z
2
3
Symbol
t
RRD
t
RCD
t
RP
t
RAS
t
RC
t
RDL
t
CDL
T
BDL
T
CCD
133MHz
Min.
15
20
20
45
67.5
8
1
1
1
133MHz
Max.
120K
100MHz
Min.
20
20
20
50
70
10
1
1
1
100MHz
Max.
Unit
ns
ns
ns
ns
ns
ns
clk
clk
clk
Ea
120K
2
-
t
CC
T
AC
t
OH
t
CH
t
CL
t
SS
t
SH
T
SLZ
2.7
-
2.5
2.5
1.5
0.8
1
7.5
-
5.4
5.4
3
3
3
3
2
1
1
10
3
10
2
1
ns
6
6
ns
ns
ns
ns
ns
ns
ns
Typical Actual values run lower that Max Spec’Ed Values.
Available for select SDRAM devices/part numbers.
Page 5
Kentron Technologies, Inc. (978) 988-9100
Rev. 4/02
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