SD-14620 SERIES
TWO-CHANNEL SYNCHRO/RESOLVER-TO-
DIGITAL CONVERTERS
AVAILA
DESCRIPTION
BLE
IN RAD AS RADIATI
ON H
-PAK
SPACE ™ TECHNO ARDENED
LO
ELECT
RONIC GY BY
S INC.
W
NE
FEATURES
• Synthesized Reference Option
The SD-14620 Series converters are
small, low-cost, two-channel hybrid
synchro- or resolver-to-digital con-
verters based on a single-chip mono-
lithic. The SD-14620XS option offers
synthesized reference circuitry to cor-
rect for phase shifts between the ref-
erence and signal inputs. The two
channels are independent but share
the digital output and +5 VDC power
pins. The package is 54-pin ceramic,
yet is the size of a 28-pin DDIP.
Resolution programming allows
selection of 10-, 12-, 14- or 16-bit
modes. This feature allows selection
of either low-resolution for fast track-
ing or higher resolution for higher
accuracy.
The velocity outputs (VEL A, VEL B) of
the SD-14620 Series, which can be
used to replace a tachometer, are ±4 V
signals referenced to analog ground.
The SD-14620 Series also offers
Built-In-Test outputs for each channel
(BIT-A, BIT-B). The converters are
available with operating temperature
ranges of 0°C to +70°C, -40°C to
+85°C and -55°C to +125°C. MIL-
PRF-38534 processing is available.
•
1 Minute Accuracy Available
(“S” Option only)
•
Single +5 V Power Supply
•
10-, 12-, 14- or 16-Bit
Programmable Resolution
APPLICATIONS
With its low-cost, small size, high
accuracy and versatile performance,
the SD-14620 Series converters are
ideal for use in modern high-perfor-
mance military, commercial and space
position control systems. Typical appli-
cations include radar antenna posi-
tioning, motor control, robotics, navi-
gation and fire control systems.
RH
RL
R
•
Small 54-Pin Ceramic Package
•
BIT Output
•
Velocity Output Replaces
Tachometer
•
High Reliability Single Chip
Monolithic
•
-55°C to +125°C Operating
Temperature Range
Available
•
MIL-PRF-38534 Processing
BIT
REFERENCE CONDITIONER
BIT
DETECTOR
LOS
"S" OPTION
SYNTHESIZED REFERENCE
C
I
ERROR
R
I
S1
S2
S3
S4
A
INPUT OPTION
CONTROL
TRANSFORMER
GAIN
B
HYSTERESIS
INTEGRATOR
DEMODULATOR
VEL
+5 V
+5 V
14/16 BIT
UP/DOWN
COUNTER
VCO & TIMING
DC-DC
CONVERTER
-5 V
FILTER
47 µf
external
capacitor
DATA LATCHES
8
8
EM DATA
EL
INH
A
B
CB
FIGURE 1. SD-14620 BLOCK DIAGRAM (ONE CHANNEL)
©
1991, 1999 Data Device Corporation
TABLE 1. SD-14620 SERIES SPECIFICATIONS (EACH CHANNEL)
These specs apply over the rated power supply, temperature, and refer-
ence frequency ranges; 10% signal amplitude variation, and 10% har-
monic distortion.
PARAMETER
UNIT
VALUE
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
SD-14620
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
SD-14620XS
Voltage Range
Frequency
Input Impedance
single ended
differential
Common-Mode Range
±Sig/Ref Phase Shift
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common-Mode Voltage
2 V Direct Input (L-L)
Voltage Range
Max. Voltage w/o Damage
Input Impedance
2 V Resolver Input (L-L)
Zin single ended
Zin differential
Common-Mode Voltage
DIGITAL INPUT/OUTPUT
Logic Type
INPUTS
Vrms
Hz
Bits
Min
LSB
LSB
programmable 10, 12, 14, or 16
±1, ±2 or ±4, + 1 LSB (see TABLE 5)
1 max.
1 max.
(RH, RL)
Each Channel
differential
2 & 11.8 V UNITS
2-35
360 - 5K
90 V UNIT
10-130
60 (47-5K)
400 (360-5K)
270K min.
540K min.
200,
300 transient
—
—
TABLE 1. SD-14620 SERIES SPECIFICATIONS (CONTINUED)
PARAMETER
DIGITAL INPUT/OUTPUT
INPUTS (continued)
Each Channel
Resolution Control
Inhibit (lNH) (common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
UNIT
VALUE
Each Channel
See TABLE 2.
Logic 0 inhibits; Data
stable within 0.5 µs
Logic 0 enables; Data stable
within 150 ns
Logic 1 = High Impedance
Data High Z within 100 ns
OUTPUTS
Parallel Data
bits
Common to all Channels
16 parallel lines; 2 bytes nat-
ural binary angle, positive
logic. (see TABLE 3)
Ohm
Ohm
Vpeak
60K
120K
50,
100 transient
2-35
1K - 5K
Each Channel
Built-In-Test
Vrms
Hz
Drive Capability
Ohm
Ohm
Vpeak
deg.
40K
80K
50,
100 transient
45 max
—
—
—
—
Each Channel
Logic 0 = BIT condition.
~ ± 100 LSBs of error with a
filter of 500 µs for LOS.
(LOS and LOR for “S” option)
TTL 50 pF +
Logic 0; 1 TTL load, 1.6 mA
at 0.4 V max
Logic 1; 10 TTL loads,
-0.4 mA at 2.8 V min
CMOS Logic 0; 100mV max.
Logic 1; +5 V supply minus
100 mV min.
Ohm 123K
Ohm 80K
V
180 max.
Ohm 52K
Ohm 34K
V
30 max.
(same for “S” option)
Ohm 140K
Ohm 70K
V
30 max.
VELOCITY CHARACTERISTICS
Each Channel
(see Note 1)
Positive for increasing angle
Polarity
4.0 typ.
3.5 min.
Voltage Range (Full Scale)
±V
10 typ.
20 max.
Scale Factor
±%
200 max.
Scale Factor TC
ppm/°C 100 typ.
1 typ.
2 max.
Reversal Error
±%
0.5 typ.
1 max.
Linearity
±%
2 typ.
3 max.
Linearity (90 V/60 Hz)
±%
5 typ.
10 max.
Zero Offset
mV
15 typ.
30 max.
Zero Offset TC
µV/°C
20 max.
Load
KOhm
2 max.
Noise
(Vp/V)% 0.125 min.
1 typ.
DC ERROR (E)
POWER SUPPLIES
Nominal Voltage
Voltage Tolerance
Max. Voltage w/o Damage
Current
TEMPERATURE RANGE
Operating
-30X
-20X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
V
-1.25 per +1 LSB error
filtered (±3 LSB range).
+5
±5
+7
60 typ.
70 max.
Vrms 2 nom, 2.3 max.
V
25 cont, 100 pk transient
Ohm 20 M || 10 pF min.
(“S” option only)
Ohm 11K
Ohm 22K
V
4.9 max.
TTL/CMOS compatible
Logic 0 = 0.8 V max.
Logic 1 = 2.0 V min.
Loading (per channel) =10 µA
max P.U. current source to
+5 V || 5 pF max.
CMOS transient protected.
V
%
V
mA
°C
°C
°C
°C
0 to +70
-40 to +85
-55 to +125
-65 to +150
in
(mm)
oz
(g)
1.50 x 0.78 x 0.21
(36.75 x 19.81 x 5.33)
0.66
(18.71)
NOTES:
1. Refer to TABLE 4 for full-scale tracking rate.
2
THEORY OF OPERATION
The SD-14620 Series of converters are based upon a single chip
CMOS custom monolithic. Using the latest technology, precision
analog circuitry is merged with digital logic to form a complete,
high-performance tracking synchro/resolver-to-digital (S/D, R/D)
converter.
GENERAL SET-UP CONSIDERATIONS
The following recommendations should be considered when
connecting the SD-14620 Series converters:
1) The +5 VDC power supply input is on pin 18. For performance
with the lowest amount of noise it is recommended that a
10 µF/10 VDC (or larger) tantalum filter capacitor be connect-
ed to ground (pin 19) near the converter package.
2) Direct inputs are referenced to Analog Ground (A GND).
Connections should made as close to the converter package
as possible to minimize noise. Channel A should be refer-
enced to A GND-A (pin 5) and Channel B should be refer-
enced to A GND-B (pin 32).
3) A 47 µF/10 V tantalum filter capacitor must be added exter-
nally from pin 52 (channel “A” filter point) to pin 19 (ground). In
addition, a 47 µF/10 Vdc tantalum filter capacitor must be
added externally from pin 24 (channel “B” filter point) to pin 19
(ground).
CONVERTER OPERATION
FIGURE 1 is the Functional Block Diagram of the SD-14620
Series. The converter operates with a single +5 VDC power sup-
ply and each channel internally generates a negative voltage of
approximately 5 volts. These negative voltages are connected to
pin 52 (channel “A” filter point) and pin 24 (channel “B” filter
point) — see GENERAL SETUP CONSIDERATIONS.
The converter is made up of three main sections; an input front-
end, an error processor, and a digital interface. The converter
front-end differs for synchro, resolver and direct inputs. An elec-
tronic Scott-T is used for synchro inputs, a resolver conditioner
for resolver inputs, and a sine and cosine voltage follower for
direct inputs. These amplifiers feed the high accuracy Control
Transformer (CT). Its other input is the 16-bit digital angle
φ.
Its
output is an analog error angle, or difference angle, between the
two inputs. The CT performs the ratiometric trigonometric com-
putation of SINθCOSφ - COSθSINφ = SIN(θ -
φ)
using amplifiers,
switches, logic, and capacitors in precision ratios. The converter
accuracy is limited by the precision of the computing elements in
the CT. Ratioed capacitors are used in the CT in these convert-
ers, instead of the more conventional precision ratioed resistors.
Capacitors that are used as computing elements with op-amps
are sampled at a high rate to eliminate drift and the op-amp off-
sets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which in turn drives a volt-
age- controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant-voltage input to position-rate output) that,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop and a lag at a higher frequency is introduced to
reduce the gain and ripple at the carrier frequency and above.
SPECIAL FUNCTIONS
PROGRAMMABLE RESOLUTION
Resolution is controlled by pins 49 and 50 for channel A; pins 21
and 22 for channel B. The resolution can be changed during con-
verter operation, so the appropriate resolution and velocity
dynamics can be changed as needed. To insure that a race con-
dition does not exist between counting and changing the resolu-
tion, the resolution control is latched internally. Refer to TABLE 2
for Channel A and B resolution control.
BIT, (BUILT-IN-TEST)
This output is an active low logic line that will flag an internal fault
condition or LOS (Loss-Of-Signal). The internal fault detector
TABLE 3. DIGITAL ANGLE OUTPUTS
BIT
1 (MSB ALL MODES)
2
3
4
5
6
7
8
9
10 (LSB 10-BIT MODE)
11
12 (LSB 12-BIT MODE)
13
14 (LSB 14-BIT MODE)
15
16 (LSB 16-BIT MODE)
DEG/BIT
180
90
45
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800
5400
2700
1350
675
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
TABLE 2. RESOLUTION CONTROL (A AND B)
RESOLUTION
B
A
10 bit
12 bit
14 bit
16 bit
0
0
1
1
0
1
0
1
Note: HBE enables the MSB byte and LBE enables the LSB byte.
3
monitors the internal loop error and, when it exceeds approximate-
ly ±100 LSBs, will set the line to a logic 0. This condition will occur
during a large-step input and will reset to a logic 1 after the con-
verter settles out. (The BIT is filtered with a 500 µs delay.) BIT will
set for an overvelocity condition because the converter loop can not
maintain input/output sync. For the “S” option only, this output will
be active low for a LOR (Loss-Of-Reference) fault condition.
NO FALSE 180° HANGUP
The converter is designed to eliminate a “false 180° reading” dur-
ing instantaneous 180° step changes. This condition most often
occurs when the input is “electronically switched” from a digital-
to-synchro converter. If the “MSB” (or 180° bit) is “toggled” on
and off, a converter without the “false 180° hangup” feature may
fail to respond. The condition is artificial, as a “real” synchro or
resolver cannot change its output 180° instantaneously. The con-
dition is most often noticed during wraparound verification tests,
simulations, or troubleshooting.
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature voltages
are not completely eliminated. As shown in FIGURE 1, the con-
verter synthesizes its own internal reference signal based on the
SIN and COS signal inputs. Therefore, the phase of the synthe-
sized (internal) reference is determined by the signal input, result-
ing in reduced quadrature errors. The synthesized reference cir-
cuit also eliminates the 180 degree false error null hang up.
INTERFACING
SOLID-STATE BUFFER PROTECTION - TRANSIENT
VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input imped-
ance is maintained with power off. The recurrent AC peak + DC
common-mode voltage should not exceed the values in TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 300 V specification listed in TABLE 1.
These tran-
sients can destroy the thin-film input resistor network in the
hybrid.
Therefore, 90 V
L-L
solid-state input modules may be
protected by installing voltage suppressors (See FIGURE 2).
Voltage transients are likely to occur whenever a synchro is
switched on and off. For instance, a 1000 V transient can be gen-
erated when the primary of a CX or TX input is opened.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while the data is being trans-
ferred. Application of an inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds (maximum) after
the application of the low-going Inhibit pulse.
SYNTHESIZED REFERENCE
The synthesized reference section (“S” option) eliminates errors
due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. Due to the inductive nature of synchros and
FOR 90 V SYNCHRO INPUTS
S3
CR1
S1
CR2
S2
RL
S1
90 V
SYNCHRO
INPUT
CR1, CR2, AND CR3 ARE 1.5kE170CA, BIPOLAR TRANSIENT
VOLTAGE SUPRESSORS OR EQUIVALENT.
CR4 IS A 1.5kE200C.
115 V
REF.
INPUT
CR3
S2
S3
RH
HYBRID
CR4
FIGURE 2. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
Output angle data is enabled onto the tri-state data bus in four
bytes. This Enable MSB (EM-A or EM-B) is used for the most sig-
nificant 8 bits and Enable LSB (EL-A or EL-B) is used for the
least significant bits. As shown in FIGURE 4, output data is valid
150 nanoseconds (maximum) after the application of a low-going
INHIBIT
EM OR EL
DATA
;; ;;;
500 ns max
DATA
VALID
150 ns MAX
DATA
HIGH Z
FIGURE 3. INHIBIT TIMING
FIGURE 4. ENABLE TIMING
4
;; ;
;; ;
DATA
VALID
100 ns MAX
HIGH Z
TABLE 4. DYNAMIC CHARACTERISTICS
EACH CHANNEL
60 Hz
Input Frequency
Bandwidth (Closed Loop)
Ka
A1
A2
A
B
Resolution
Tracking Rate (rps)
typical
minimum
Acceleration ( 1 LSB lag)
Settling Time (179° step max)
Hz
Hz
1/s
2
1/s
1/s
1/s
1/s
BITS
rps
rps
deg/s
2
msec
10
32
25.6
720
400
47 - 5K
15
830
0.17
5K
29
14.5
12
8
6.4
180
500
14
2
1.6
45
1100
16
0.5
0.4
11.3
2500
10
160
128
5950
90
DEVICE TYPE
400 Hz
360 - 5K
56
53K
0.41
41K
130
81
12
40
32
1490
100
14
10
8
372
180
16
2.5
2
93
360
10
160
128
39K
51
“S” OPTION
1K - 5K
150
110K
2.47
44.4K
333
166
12
40
32
9760
78
14
10
8
2440
150
16
2.5
2
610
232
TRANSFER FUNCTION AND BODE PLOT
enable pulse. The tri-state data bus returns to the high imped-
ance state 100 nanoseconds (maximum) after the rising edge of
the enable signal.
The dynamic performance of the converter can be determined
from its Functional Block Diagram (FIGURE 1), its transfer func-
tion block diagram (FIGURE 5), and its Bode Plots (open and
closed loop - FIGURE 6). Values for the transfer function block
can be obtained from TABLE 4.
The open loop transfer function is as follows:
DYNAMIC PERFORMANCE
A type II servo loop (Kv =
∞)
and very high acceleration con-
stants give the SD-14620 superior dynamic performance.
TABLE 5. ACCURACY/RESOLUTION
VERSION
SD-1462X-XX
SD-1462X-XS
(“S” option)
ACCURACY
(minutes)
±4 +1 LSB
±2 +1 LSB
±4 +1 LSB
±2 +1 LSB
±1 +1 LSB
RESOLUTION (minutes)
10 BIT
42.2
42.2
25.1
23.1
22.1
12 BIT
10.5
10.5
9.3
7.3
6.3
14 BIT
5.3
3.3
5.3
3.3
2.3
16 BIT
4.3
2.3
4.3
2.3
* 1.3
A
2
S +1
B
Open Loop Transfer Function =
S
2
S +1
10B
(
(
)
)
where A is the gain coefficient
and B is the frequency of lead compensation
ACCURACY AND RESOLUTION
TABLE 5 lists the total accuracy including quantification of the
various resolutions and accuracy grades.
* 1.3 minute accuracy available for “S” option only.
Inclusive of 1 bit of jitter.
-1
ERROR PROCESSOR
INPUT
(θ)
+
-
CT
e
A1 S + 1
B
S
S +1
10B
VELOCITY
OUT
VCO
A
2
S
DIGITAL
POSITION
OUT (φ)
GAIN = 4
OPEN LOOP
2d
B/
oc
(CRITICALLY DAMPED)
2A
ω
(rad/sec)
10B
- GAIN = 0.4
f
3dB
= BW =
2 A (Hz)
π
B
A
(B=A/2)
t
-6
dB
/oc
t
H=1
A
2
S +1
B
Open Loop Transfer Function =
2
S +1
S
10B
(
(
)
)
WHERE:
A
2
= A
1
A
2
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 5. TRANSFER FUNCTION BLOCK DIAGRAM
FIGURE 6. BODE PLOTS
5
Wireless Connectivity
京公网安备 11010802033920号
EEWORLD
